14ae8bc43SStefan Roese/* 24ae8bc43SStefan Roese * armboot - Startup Code for ARM926EJS CPU-core 34ae8bc43SStefan Roese * 44ae8bc43SStefan Roese * Copyright (c) 2003 Texas Instruments 54ae8bc43SStefan Roese * 64ae8bc43SStefan Roese * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 74ae8bc43SStefan Roese * 84ae8bc43SStefan Roese * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 94ae8bc43SStefan Roese * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 104ae8bc43SStefan Roese * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 114ae8bc43SStefan Roese * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 124ae8bc43SStefan Roese * Copyright (c) 2003 Kshitij <kshitij@ti.com> 134ae8bc43SStefan Roese * 141a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 154ae8bc43SStefan Roese */ 164ae8bc43SStefan Roese 174ae8bc43SStefan Roese 184ae8bc43SStefan Roese#include <config.h> 194ae8bc43SStefan Roese 204ae8bc43SStefan Roese/* 214ae8bc43SStefan Roese ************************************************************************* 224ae8bc43SStefan Roese * 234ae8bc43SStefan Roese * Startup Code (reset vector) 244ae8bc43SStefan Roese * 254ae8bc43SStefan Roese * Below are the critical initializations already taken place in BootROM. 264ae8bc43SStefan Roese * So, these are not taken care in Xloader 274ae8bc43SStefan Roese * 1. Relocation to RAM 284ae8bc43SStefan Roese * 2. Initializing stacks 294ae8bc43SStefan Roese * 304ae8bc43SStefan Roese ************************************************************************* 314ae8bc43SStefan Roese */ 324ae8bc43SStefan Roese 3341623c91SAlbert ARIBAUD .globl reset 344ae8bc43SStefan Roese 354ae8bc43SStefan Roesereset: 364ae8bc43SStefan Roese/* 374ae8bc43SStefan Roese * Xloader has to return back to BootROM in a few cases. 384ae8bc43SStefan Roese * eg. Ethernet boot, UART boot, USB boot 394ae8bc43SStefan Roese * Saving registers for returning back 404ae8bc43SStefan Roese */ 414ae8bc43SStefan Roese stmdb sp!, {r0-r12,r14} 424ae8bc43SStefan Roese bl cpu_init_crit 434ae8bc43SStefan Roese/* 444ae8bc43SStefan Roese * Clearing bss area is not done in Xloader. 454ae8bc43SStefan Roese * BSS area lies in the DDR location which is not yet initialized 464ae8bc43SStefan Roese * bss is assumed to be uninitialized. 474ae8bc43SStefan Roese */ 484ae8bc43SStefan Roese ldmia sp!, {r0-r12,pc} 494ae8bc43SStefan Roese 504ae8bc43SStefan Roese/* 514ae8bc43SStefan Roese ************************************************************************* 524ae8bc43SStefan Roese * 534ae8bc43SStefan Roese * CPU_init_critical registers 544ae8bc43SStefan Roese * 554ae8bc43SStefan Roese * setup important registers 564ae8bc43SStefan Roese * setup memory timing 574ae8bc43SStefan Roese * 584ae8bc43SStefan Roese ************************************************************************* 594ae8bc43SStefan Roese */ 604ae8bc43SStefan Roesecpu_init_crit: 614ae8bc43SStefan Roese /* 624ae8bc43SStefan Roese * flush v4 I/D caches 634ae8bc43SStefan Roese */ 644ae8bc43SStefan Roese mov r0, #0 654ae8bc43SStefan Roese mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 664ae8bc43SStefan Roese mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 674ae8bc43SStefan Roese 684ae8bc43SStefan Roese /* 694ae8bc43SStefan Roese * enable instruction cache 704ae8bc43SStefan Roese */ 714ae8bc43SStefan Roese mrc p15, 0, r0, c1, c0, 0 724ae8bc43SStefan Roese orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 734ae8bc43SStefan Roese mcr p15, 0, r0, c1, c0, 0 744ae8bc43SStefan Roese 754ae8bc43SStefan Roese /* 764ae8bc43SStefan Roese * Go setup Memory and board specific bits prior to relocation. 774ae8bc43SStefan Roese */ 784ae8bc43SStefan Roese stmdb sp!, {lr} 79*2fbdbda1SStefan Roese bl _main /* _main will call board_init_f */ 804ae8bc43SStefan Roese ldmia sp!, {pc} 81