184ad6884SPeter Tyser/* 2678e008cSCyril Chemparathy * armboot - Startup Code for ARM1176 CPU-core 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (c) 2007 Samsung Electronics 584ad6884SPeter Tyser * 684ad6884SPeter Tyser * Copyright (C) 2008 784ad6884SPeter Tyser * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 884ad6884SPeter Tyser * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1084ad6884SPeter Tyser * 1184ad6884SPeter Tyser * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 1284ad6884SPeter Tyser * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 1384ad6884SPeter Tyser * jsgood (jsgood.yang@samsung.com) 1484ad6884SPeter Tyser * Base codes by scsuh (sc.suh) 1584ad6884SPeter Tyser */ 1684ad6884SPeter Tyser 1725ddd1fbSWolfgang Denk#include <asm-offsets.h> 1884ad6884SPeter Tyser#include <config.h> 19*3e10fcdeSCédric Schieli#include <linux/linkage.h> 2084ad6884SPeter Tyser 219ce8e238SBenoît Thébaudeau#ifndef CONFIG_SYS_PHY_UBOOT_BASE 2284ad6884SPeter Tyser#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 2384ad6884SPeter Tyser#endif 2484ad6884SPeter Tyser 2584ad6884SPeter Tyser/* 2684ad6884SPeter Tyser ************************************************************************* 2784ad6884SPeter Tyser * 2884ad6884SPeter Tyser * Startup Code (reset vector) 2984ad6884SPeter Tyser * 3084ad6884SPeter Tyser * do important init only if we don't start from memory! 3184ad6884SPeter Tyser * setup Memory and board specific bits prior to relocation. 3284ad6884SPeter Tyser * relocate armboot to ram 3384ad6884SPeter Tyser * setup stack 3484ad6884SPeter Tyser * 3584ad6884SPeter Tyser ************************************************************************* 3684ad6884SPeter Tyser */ 3784ad6884SPeter Tyser 3841623c91SAlbert ARIBAUD .globl reset 39a51dd67aSHeiko Schocher 40a51dd67aSHeiko Schocherreset: 41*3e10fcdeSCédric Schieli /* Allow the board to save important registers */ 42*3e10fcdeSCédric Schieli b save_boot_params 43*3e10fcdeSCédric Schieli.globl save_boot_params_ret 44*3e10fcdeSCédric Schielisave_boot_params_ret: 45*3e10fcdeSCédric Schieli 46a51dd67aSHeiko Schocher /* 47a51dd67aSHeiko Schocher * set the cpu to SVC32 mode 48a51dd67aSHeiko Schocher */ 49a51dd67aSHeiko Schocher mrs r0, cpsr 50a51dd67aSHeiko Schocher bic r0, r0, #0x3f 51a51dd67aSHeiko Schocher orr r0, r0, #0xd3 52a51dd67aSHeiko Schocher msr cpsr, r0 53a51dd67aSHeiko Schocher 54a51dd67aSHeiko Schocher/* 55a51dd67aSHeiko Schocher ************************************************************************* 56a51dd67aSHeiko Schocher * 57a51dd67aSHeiko Schocher * CPU_init_critical registers 58a51dd67aSHeiko Schocher * 59a51dd67aSHeiko Schocher * setup important registers 60a51dd67aSHeiko Schocher * setup memory timing 61a51dd67aSHeiko Schocher * 62a51dd67aSHeiko Schocher ************************************************************************* 63a51dd67aSHeiko Schocher */ 64a51dd67aSHeiko Schocher /* 65a51dd67aSHeiko Schocher * we do sys-critical inits only at reboot, 66a51dd67aSHeiko Schocher * not when booting from ram! 67a51dd67aSHeiko Schocher */ 68a51dd67aSHeiko Schochercpu_init_crit: 69a51dd67aSHeiko Schocher /* 70a51dd67aSHeiko Schocher * When booting from NAND - it has definitely been a reset, so, no need 71a51dd67aSHeiko Schocher * to flush caches and disable the MMU 72a51dd67aSHeiko Schocher */ 7366f30bf9SBenoît Thébaudeau#ifndef CONFIG_SPL_BUILD 74a51dd67aSHeiko Schocher /* 75a51dd67aSHeiko Schocher * flush v4 I/D caches 76a51dd67aSHeiko Schocher */ 77a51dd67aSHeiko Schocher mov r0, #0 78a51dd67aSHeiko Schocher mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 79a51dd67aSHeiko Schocher mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 80a51dd67aSHeiko Schocher 81a51dd67aSHeiko Schocher /* 82a51dd67aSHeiko Schocher * disable MMU stuff and caches 83a51dd67aSHeiko Schocher */ 84a51dd67aSHeiko Schocher mrc p15, 0, r0, c1, c0, 0 85a51dd67aSHeiko Schocher bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 86a51dd67aSHeiko Schocher bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 87ba10b852SYuichiro Goto orr r0, r0, #0x00000002 @ set bit 1 (A) Align 88a51dd67aSHeiko Schocher orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 89a51dd67aSHeiko Schocher 90a51dd67aSHeiko Schocher /* Prepare to disable the MMU */ 91a51dd67aSHeiko Schocher adr r2, mmu_disable_phys 9214d0a02aSWolfgang Denk sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 93a51dd67aSHeiko Schocher b mmu_disable 94a51dd67aSHeiko Schocher 95a51dd67aSHeiko Schocher .align 5 96a51dd67aSHeiko Schocher /* Run in a single cache-line */ 97a51dd67aSHeiko Schochermmu_disable: 98a51dd67aSHeiko Schocher mcr p15, 0, r0, c1, c0, 0 99a51dd67aSHeiko Schocher nop 100a51dd67aSHeiko Schocher nop 101a51dd67aSHeiko Schocher mov pc, r2 102a51dd67aSHeiko Schochermmu_disable_phys: 103a51dd67aSHeiko Schocher 104a51dd67aSHeiko Schocher#endif 105a51dd67aSHeiko Schocher 106a51dd67aSHeiko Schocher /* 107a51dd67aSHeiko Schocher * Go setup Memory and board specific bits prior to relocation. 108a51dd67aSHeiko Schocher */ 109a51dd67aSHeiko Schocher bl lowlevel_init /* go setup pll,mux,memory */ 110a51dd67aSHeiko Schocher 111e05e5de7SAlbert ARIBAUD bl _main 112a51dd67aSHeiko Schocher 113a51dd67aSHeiko Schocher/*------------------------------------------------------------------------------*/ 114a51dd67aSHeiko Schocher 115e05e5de7SAlbert ARIBAUD .globl c_runtime_cpu_setup 116e05e5de7SAlbert ARIBAUDc_runtime_cpu_setup: 117e05e5de7SAlbert ARIBAUD 118e05e5de7SAlbert ARIBAUD mov pc, lr 119*3e10fcdeSCédric Schieli 120*3e10fcdeSCédric SchieliWEAK(save_boot_params) 121*3e10fcdeSCédric Schieli b save_boot_params_ret /* back to my caller */ 122*3e10fcdeSCédric SchieliENDPROC(save_boot_params) 123