arch: arm: Add ARM_ERRATA_814220

Sync from kernel.

- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.

- Implications:
Code that intends to clean dirty data from L1

arch: arm: Add ARM_ERRATA_814220

Sync from kernel.

- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.

- Implications:
Code that intends to clean dirty data from L1 to L2 and then from L2 to L3 using
set/way operations might not behave as expected. The L2 to L3 operation might
happen first and result in dirty data remaining in L2 after the L1 to L2 operation
has completed.
If dirty data remains in L2 then an external agent, such as a DMA agent, might
observe stale data.
If the processor is reset or powered-down while dirty data remains in L2 then
the dirty data will be lost.

- Workaround:
Correct ordering between set/way cache maintenance operations can be forced by
executing a DSB before changing cache levels.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide0a03b891cfa471f7cee2033430a02f2c5ec59b

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arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only

arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only build SPL in Thumb2 mode due
to size constraints and wish to build the rest of the system in ARM mode. So
in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to
control if we build everything or just SPL (or in theory, just U-Boot) in
Thumb2 mode.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>

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arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with asm code

Lets be consistent and also replace v7_maint_dcache_all()
with asm code for the invalidate case.

Signed-off-by: Hans de Goede

arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with asm code

Lets be consistent and also replace v7_maint_dcache_all()
with asm code for the invalidate case.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

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arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL) with asm code

v7_maint_dcache_all() does not work reliable when build with gcc6,
see: https://bugzilla.redhat.com/show_bug.cgi?id=13187

arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL) with asm code

v7_maint_dcache_all() does not work reliable when build with gcc6,
see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788

While debugging this I learned that v7_maint_dcache_all() is unreliable
when build with gcc5 too when it is marked as noinline.

This commit fixes the reliability issues by replacing the C-code with
the ready to use asm implementation from the kernel.

Given that this code when written as C-code clearly is quite fragile
(also see the existing comments about the C-code being the way it is
to get optimal assembly) and that we have a proven asm alternative,
I believe that this is the best solution.

Note that we actually already had a copy of the kernel's
v7_flush_dcache_all() before this commit in
arch/arm/mach-uniphier/arm32/lowlevel_init.S.

This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames
it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper
which saves / restores the clobbered registers for use from C-code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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