184ad6884SPeter Tyser/* 284ad6884SPeter Tyser * armboot - Startup Code for SA1100 CPU 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 584ad6884SPeter Tyser * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 684ad6884SPeter Tyser * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7fa82f871SAlbert ARIBAUD * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 884ad6884SPeter Tyser * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1084ad6884SPeter Tyser */ 1184ad6884SPeter Tyser 1225ddd1fbSWolfgang Denk#include <asm-offsets.h> 1384ad6884SPeter Tyser#include <config.h> 1484ad6884SPeter Tyser 1584ad6884SPeter Tyser/* 1684ad6884SPeter Tyser ************************************************************************* 1784ad6884SPeter Tyser * 1884ad6884SPeter Tyser * Startup Code (reset vector) 1984ad6884SPeter Tyser * 2084ad6884SPeter Tyser * do important init only if we don't start from memory! 2184ad6884SPeter Tyser * relocate armboot to ram 2284ad6884SPeter Tyser * setup stack 2384ad6884SPeter Tyser * jump to second stage 2484ad6884SPeter Tyser * 2584ad6884SPeter Tyser ************************************************************************* 2684ad6884SPeter Tyser */ 2784ad6884SPeter Tyser 2841623c91SAlbert ARIBAUD .globl reset 29e30ceca2SHeiko Schocher 30e30ceca2SHeiko Schocherreset: 31e30ceca2SHeiko Schocher /* 32e30ceca2SHeiko Schocher * set the cpu to SVC32 mode 33e30ceca2SHeiko Schocher */ 34e30ceca2SHeiko Schocher mrs r0,cpsr 35e30ceca2SHeiko Schocher bic r0,r0,#0x1f 36e30ceca2SHeiko Schocher orr r0,r0,#0xd3 37e30ceca2SHeiko Schocher msr cpsr,r0 38e30ceca2SHeiko Schocher 39e30ceca2SHeiko Schocher /* 40e30ceca2SHeiko Schocher * we do sys-critical inits only at reboot, 41e30ceca2SHeiko Schocher * not when booting from ram! 42e30ceca2SHeiko Schocher */ 43e30ceca2SHeiko Schocher#ifndef CONFIG_SKIP_LOWLEVEL_INIT 44e30ceca2SHeiko Schocher bl cpu_init_crit 45e30ceca2SHeiko Schocher#endif 46e30ceca2SHeiko Schocher 47e05e5de7SAlbert ARIBAUD bl _main 48e30ceca2SHeiko Schocher 49e30ceca2SHeiko Schocher/*------------------------------------------------------------------------------*/ 50e30ceca2SHeiko Schocher 51e05e5de7SAlbert ARIBAUD .globl c_runtime_cpu_setup 52e05e5de7SAlbert ARIBAUDc_runtime_cpu_setup: 53e05e5de7SAlbert ARIBAUD 54e05e5de7SAlbert ARIBAUD mov pc, lr 55e05e5de7SAlbert ARIBAUD 5684ad6884SPeter Tyser/* 5784ad6884SPeter Tyser ************************************************************************* 5884ad6884SPeter Tyser * 5984ad6884SPeter Tyser * CPU_init_critical registers 6084ad6884SPeter Tyser * 6184ad6884SPeter Tyser * setup important registers 6284ad6884SPeter Tyser * setup memory timing 6384ad6884SPeter Tyser * 6484ad6884SPeter Tyser ************************************************************************* 6584ad6884SPeter Tyser */ 6684ad6884SPeter Tyser 6784ad6884SPeter Tyser 6816263087SMike Williams/* Interrupt-Controller base address */ 6984ad6884SPeter TyserIC_BASE: .word 0x90050000 7084ad6884SPeter Tyser#define ICMR 0x04 7184ad6884SPeter Tyser 7284ad6884SPeter Tyser 7384ad6884SPeter Tyser/* Reset-Controller */ 7484ad6884SPeter TyserRST_BASE: .word 0x90030000 7584ad6884SPeter Tyser#define RSRR 0x00 7684ad6884SPeter Tyser#define RCSR 0x04 7784ad6884SPeter Tyser 7884ad6884SPeter Tyser 7984ad6884SPeter Tyser/* PWR */ 8084ad6884SPeter TyserPWR_BASE: .word 0x90020000 8184ad6884SPeter Tyser#define PSPR 0x08 8284ad6884SPeter Tyser#define PPCR 0x14 8384ad6884SPeter Tysercpuspeed: .word CONFIG_SYS_CPUSPEED 8484ad6884SPeter Tyser 8584ad6884SPeter Tyser 8684ad6884SPeter Tysercpu_init_crit: 8784ad6884SPeter Tyser /* 8884ad6884SPeter Tyser * mask all IRQs 8984ad6884SPeter Tyser */ 9084ad6884SPeter Tyser ldr r0, IC_BASE 9184ad6884SPeter Tyser mov r1, #0x00 9284ad6884SPeter Tyser str r1, [r0, #ICMR] 9384ad6884SPeter Tyser 9484ad6884SPeter Tyser /* set clock speed */ 9584ad6884SPeter Tyser ldr r0, PWR_BASE 9684ad6884SPeter Tyser ldr r1, cpuspeed 9784ad6884SPeter Tyser str r1, [r0, #PPCR] 9884ad6884SPeter Tyser 99*b5bd0982SSimon Glass#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 10084ad6884SPeter Tyser /* 10184ad6884SPeter Tyser * before relocating, we have to setup RAM timing 10284ad6884SPeter Tyser * because memory timing is board-dependend, you will 10384ad6884SPeter Tyser * find a lowlevel_init.S in your board directory. 10484ad6884SPeter Tyser */ 10584ad6884SPeter Tyser mov ip, lr 10684ad6884SPeter Tyser bl lowlevel_init 10784ad6884SPeter Tyser mov lr, ip 108*b5bd0982SSimon Glass#endif 10984ad6884SPeter Tyser 11084ad6884SPeter Tyser /* 11184ad6884SPeter Tyser * disable MMU stuff and enable I-cache 11284ad6884SPeter Tyser */ 11384ad6884SPeter Tyser mrc p15,0,r0,c1,c0 11484ad6884SPeter Tyser bic r0, r0, #0x00002000 @ clear bit 13 (X) 11584ad6884SPeter Tyser bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 11684ad6884SPeter Tyser orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 117ba10b852SYuichiro Goto orr r0, r0, #0x00000002 @ set bit 1 (A) Align 11884ad6884SPeter Tyser mcr p15,0,r0,c1,c0 11984ad6884SPeter Tyser 12084ad6884SPeter Tyser /* 12184ad6884SPeter Tyser * flush v4 I/D caches 12284ad6884SPeter Tyser */ 12384ad6884SPeter Tyser mov r0, #0 12484ad6884SPeter Tyser mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 12584ad6884SPeter Tyser mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 12684ad6884SPeter Tyser 12784ad6884SPeter Tyser mov pc, lr 128