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Searched refs:dram (Results 1 – 25 of 62) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c61 struct sunxi_dram_reg *dram = in mctl_ddr3_reset() local
74 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
76 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
80 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
82 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
101 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; in mctl_set_drive() local
104 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), in mctl_set_drive()
106 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), in mctl_set_drive()
114 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; in mctl_itm_disable() local
116 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); in mctl_itm_disable()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c28 void ddr_init(struct emc_dram_settings *dram) in ddr_init() argument
40 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()
41 writel(dram->config0, &emc->config0); in ddr_init()
42 writel(dram->rascas0, &emc->rascas0); in ddr_init()
43 writel(dram->rdconfig, &emc->read_config); in ddr_init()
45 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
46 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
47 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); in ddr_init()
48 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); in ddr_init()
49 writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); in ddr_init()
[all …]
H A DMakefile10 obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_px30.c65 static void rkclk_ddr_reset(struct dram_info *dram, in rkclk_ddr_reset() argument
71 &dram->cru->softrst_con[1]); in rkclk_ddr_reset()
73 &dram->cru->softrst_con[2]); in rkclk_ddr_reset()
76 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll() argument
104 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); in rkclk_set_dpll()
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
108 &dram->cru->pll[1].con1); in rkclk_set_dpll()
112 if (LOCK(readl(&dram->cru->pll[1].con1))) in rkclk_set_dpll()
117 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); in rkclk_set_dpll()
120 static void rkclk_configure_ddr(struct dram_info *dram, in rkclk_configure_ddr() argument
[all …]
H A Dsdram_rk3328.c67 static void rkclk_ddr_reset(struct dram_info *dram, in rkclk_ddr_reset() argument
73 &dram->cru->softrst_con[5]); in rkclk_ddr_reset()
74 writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]); in rkclk_ddr_reset()
77 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll() argument
105 writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con); in rkclk_set_dpll()
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); in rkclk_set_dpll()
108 &dram->cru->dpll_con[1]); in rkclk_set_dpll()
112 if (LOCK(readl(&dram->cru->dpll_con[1]))) in rkclk_set_dpll()
117 writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con); in rkclk_set_dpll()
120 static void rkclk_configure_ddr(struct dram_info *dram, in rkclk_configure_ddr() argument
[all …]
H A Dsdram_rv1126.c309 static void rkclk_ddr_reset(struct dram_info *dram, in rkclk_ddr_reset() argument
318 &dram->cru->softrst_con[12]); in rkclk_ddr_reset()
321 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll() argument
357 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); in rkclk_set_dpll()
359 writel(0x1f000000, &dram->cru->clksel_con[64]); in rkclk_set_dpll()
360 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
364 clrsetbits_le32(&dram->cru->pll[1].con2, in rkclk_set_dpll()
372 &dram->cru->pll[1].con3); in rkclk_set_dpll()
375 &dram->cru->pll[1].con1); in rkclk_set_dpll()
379 if (LOCK(readl(&dram->cru->pll[1].con1))) in rkclk_set_dpll()
[all …]
H A Dsdram_rk322x.c363 static void phy_softreset(struct dram_info *dram) in phy_softreset() argument
365 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in phy_softreset()
366 struct rk322x_grf *grf = dram->grf; in phy_softreset()
378 static void set_bw(struct dram_info *dram, u32 bw) in set_bw() argument
380 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; in set_bw()
381 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in set_bw()
382 struct rk322x_grf *grf = dram->grf; in set_bw()
577 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
595 writel(sys_reg, &dram->grf->os_reg[2]); in dram_all_config()
600 static int dram_cap_detect(struct dram_info *dram, in dram_cap_detect() argument
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H A Dsdram_rk3399.c773 static void pctl_start(struct dram_info *dram, in pctl_start() argument
777 const struct chan_info *chan_0 = &dram->chan[0]; in pctl_start()
778 const struct chan_info *chan_1 = &dram->chan[1]; in pctl_start()
788 writel(0x01000000, &dram->grf->ddrc0_con0); in pctl_start()
804 writel(0x01000100, &dram->grf->ddrc0_con0); in pctl_start()
825 writel(0x01000000, &dram->grf->ddrc1_con0); in pctl_start()
840 writel(0x01000100, &dram->grf->ddrc1_con0); in pctl_start()
1813 static void dram_all_config(struct dram_info *dram, in dram_all_config() argument
1832 ddr_msch_regs = dram->chan[channel].msch; in dram_all_config()
1838 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], in dram_all_config()
[all …]
H A DKconfig4 This enable dram devfreq driver.
20 bool "enable rockchip dram extended temperature support"
24 This enable dram dram extended temperature support
H A Dsdram_rk3188.c535 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
557 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
560 ddr_rank_2_row15en(dram->grf, 0); in dram_all_config()
562 ddr_rank_2_row15en(dram->grf, 1); in dram_all_config()
564 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
567 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
572 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
575 ddr_rank_2_row15en(dram->grf, 0); in sdram_rank_bw_detect()
598 dram->grf); in sdram_rank_bw_detect()
608 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
[all …]
H A Dsdram_rk3288.c592 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
614 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
616 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
617 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); in dram_all_config()
620 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
625 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
651 dram->grf); in sdram_rank_bw_detect()
661 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
663 ddr_phy_ctl_reset(dram->cru, channel, 0); in sdram_rank_bw_detect()
673 static int sdram_col_row_detect(struct dram_info *dram, int channel, in sdram_col_row_detect() argument
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/
H A DMakefile7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
9 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
10 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
11 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
12 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
/rk3399_rockchip-uboot/arch/x86/dts/
H A Dgalileo.dts51 dram-width = <DRAM_WIDTH_X8>;
52 dram-speed = <DRAM_FREQ_800>;
53 dram-type = <DRAM_TYPE_DDR3>;
63 dram-density = <DRAM_DENSITY_1G>;
64 dram-cl = <6>;
65 dram-ras = <0x0000927c>;
66 dram-wtr = <0x00002710>;
67 dram-rrd = <0x00002710>;
68 dram-faw = <0x00009c40>;
/rk3399_rockchip-uboot/drivers/mmc/
H A Dmv_sdhci.c17 const struct mbus_dram_target_info *dram; in sdhci_mvebu_mbus_config() local
20 dram = mvebu_mbus_dram_info(); in sdhci_mvebu_mbus_config()
27 for (i = 0; i < dram->num_cs; i++) { in sdhci_mvebu_mbus_config()
28 const struct mbus_dram_window *cs = dram->cs + i; in sdhci_mvebu_mbus_config()
32 (dram->mbus_dram_target_id << 4) | 1, in sdhci_mvebu_mbus_config()
/rk3399_rockchip-uboot/drivers/ata/
H A Dmvsata_ide.c108 const struct mbus_dram_target_info *dram; in mvsata_ide_conf_mbus_windows() local
111 dram = mvebu_mbus_dram_info(); in mvsata_ide_conf_mbus_windows()
119 for (i = 0; i < dram->num_cs; i++) { in mvsata_ide_conf_mbus_windows()
120 const struct mbus_dram_window *cs = dram->cs + i; in mvsata_ide_conf_mbus_windows()
122 (dram->mbus_dram_target_id << 4) | 1, in mvsata_ide_conf_mbus_windows()
/rk3399_rockchip-uboot/drivers/usb/host/
H A Dehci-marvell.c56 const struct mbus_dram_target_info *dram; in usb_brg_adrdec_setup() local
59 dram = mvebu_mbus_dram_info(); in usb_brg_adrdec_setup()
66 for (i = 0; i < dram->num_cs; i++) { in usb_brg_adrdec_setup()
67 const struct mbus_dram_window *cs = dram->cs + i; in usb_brg_adrdec_setup()
71 (dram->mbus_dram_target_id << 4) | 1, in usb_brg_adrdec_setup()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c522 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
544 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
547 ddr_rank_2_row15en(dram->grf, 0); in dram_all_config()
549 ddr_rank_2_row15en(dram->grf, 1); in dram_all_config()
551 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
554 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
559 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
562 ddr_rank_2_row15en(dram->grf, 0); in sdram_rank_bw_detect()
585 dram->grf); in sdram_rank_bw_detect()
595 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
[all …]
/rk3399_rockchip-uboot/drivers/video/
H A Dmvebu_lcd.c79 const struct mbus_dram_target_info *dram; in mvebu_lcd_conf_mbus_registers() local
82 dram = mvebu_mbus_dram_info(); in mvebu_lcd_conf_mbus_registers()
92 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
93 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
95 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/
H A DMakefile18 obj-y = dram.o
25 obj-y += dram.o
H A Dcpu.c498 const struct mbus_dram_target_info *dram; in ahci_mvebu_mbus_config() local
501 dram = mvebu_mbus_dram_info(); in ahci_mvebu_mbus_config()
509 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
510 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
513 (dram->mbus_dram_target_id << 4) | 1, in ahci_mvebu_mbus_config()
/rk3399_rockchip-uboot/arch/mips/mach-bmips/
H A DMakefile5 obj-y += dram.o
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/armada100/
H A DMakefile9 obj-y = cpu.o timer.o dram.o
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-lpc32xx/
H A Dsys_proto.h21 void ddr_init(const struct emc_dram_settings *dram);
/rk3399_rockchip-uboot/arch/x86/cpu/qemu/
H A DMakefile8 obj-y += car.o dram.o
/rk3399_rockchip-uboot/arch/mips/mach-ath79/
H A DMakefile7 obj-y += dram.o

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