Lines Matching refs:dram
309 static void rkclk_ddr_reset(struct dram_info *dram, in rkclk_ddr_reset() argument
318 &dram->cru->softrst_con[12]); in rkclk_ddr_reset()
321 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll() argument
357 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); in rkclk_set_dpll()
359 writel(0x1f000000, &dram->cru->clksel_con[64]); in rkclk_set_dpll()
360 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
364 clrsetbits_le32(&dram->cru->pll[1].con2, in rkclk_set_dpll()
372 &dram->cru->pll[1].con3); in rkclk_set_dpll()
375 &dram->cru->pll[1].con1); in rkclk_set_dpll()
379 if (LOCK(readl(&dram->cru->pll[1].con1))) in rkclk_set_dpll()
386 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); in rkclk_set_dpll()
389 static void rkclk_configure_ddr(struct dram_info *dram, in rkclk_configure_ddr() argument
393 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); in rkclk_configure_ddr()
501 static void sw_set_req(struct dram_info *dram) in sw_set_req() argument
503 void __iomem *pctl_base = dram->pctl; in sw_set_req()
509 static void sw_set_ack(struct dram_info *dram) in sw_set_ack() argument
511 void __iomem *pctl_base = dram->pctl; in sw_set_ack()
523 static void set_ctl_address_map(struct dram_info *dram, in set_ctl_address_map() argument
527 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
564 static void phy_pll_set(struct dram_info *dram, u32 freq, u32 wait) in phy_pll_set() argument
566 void __iomem *phy_base = dram->phy; in phy_pll_set()
812 static void set_lp4_vref(struct dram_info *dram, struct lp4_info *lp4_info, in set_lp4_vref() argument
815 void __iomem *pctl_base = dram->pctl; in set_lp4_vref()
870 sw_set_req(dram); in set_lp4_vref()
880 sw_set_ack(dram); in set_lp4_vref()
883 static void set_ds_odt(struct dram_info *dram, in set_ds_odt() argument
886 void __iomem *phy_base = dram->phy; in set_ds_odt()
887 void __iomem *pctl_base = dram->pctl; in set_ds_odt()
1090 set_lp4_vref(dram, lp4_info, freq, dst_fsp, dramtype); in set_ds_odt()
1176 sw_set_req(dram); in set_ds_odt()
1181 sw_set_ack(dram); in set_ds_odt()
1199 sw_set_req(dram); in set_ds_odt()
1204 sw_set_ack(dram); in set_ds_odt()
1208 sw_set_req(dram); in set_ds_odt()
1213 sw_set_ack(dram); in set_ds_odt()
1215 sw_set_req(dram); in set_ds_odt()
1220 sw_set_ack(dram); in set_ds_odt()
1224 static int sdram_cmd_dq_path_remap(struct dram_info *dram, in sdram_cmd_dq_path_remap() argument
1227 void __iomem *phy_base = dram->phy; in sdram_cmd_dq_path_remap()
1247 static void phy_cfg(struct dram_info *dram, in phy_cfg() argument
1251 void __iomem *phy_base = dram->phy; in phy_cfg()
1255 sdram_cmd_dq_path_remap(dram, sdram_params); in phy_cfg()
1257 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 0); in phy_cfg()
1300 static int update_refresh_reg(struct dram_info *dram) in update_refresh_reg() argument
1302 void __iomem *pctl_base = dram->pctl; in update_refresh_reg()
1315 u32 read_mr(struct dram_info *dram, u32 rank, u32 byte, u32 mr_num, u32 dramtype) in read_mr() argument
1319 void __iomem *pctl_base = dram->pctl; in read_mr()
1326 temp = (readl(&dram->ddrgrf->ddr_grf_status[0]) >> (byte * 8)) & 0xff; in read_mr()
1340 ret = (readl(&dram->ddrgrf->ddr_grf_status[1]) >> (byte * 8)) & 0xff; in read_mr()
1346 static void enter_sr(struct dram_info *dram, u32 en) in enter_sr() argument
1348 void __iomem *pctl_base = dram->pctl; in enter_sr()
1369 void record_dq_prebit(struct dram_info *dram) in record_dq_prebit() argument
1372 void __iomem *phy_base = dram->phy; in record_dq_prebit()
1393 static void update_dq_rx_prebit(struct dram_info *dram) in update_dq_rx_prebit() argument
1395 void __iomem *phy_base = dram->phy; in update_dq_rx_prebit()
1403 static void update_dq_tx_prebit(struct dram_info *dram) in update_dq_tx_prebit() argument
1405 void __iomem *phy_base = dram->phy; in update_dq_tx_prebit()
1414 static void update_ca_prebit(struct dram_info *dram) in update_ca_prebit() argument
1416 void __iomem *phy_base = dram->phy; in update_ca_prebit()
1430 static void modify_ca_deskew(struct dram_info *dram, u32 dir, int delta_dif, in modify_ca_deskew() argument
1433 void __iomem *phy_base = dram->phy; in modify_ca_deskew()
1449 enter_sr(dram, 1); in modify_ca_deskew()
1472 update_ca_prebit(dram); in modify_ca_deskew()
1474 enter_sr(dram, 0); in modify_ca_deskew()
1481 static u32 get_min_value(struct dram_info *dram, u32 signal, u32 rank) in get_min_value() argument
1485 void __iomem *phy_base = dram->phy; in get_min_value()
1510 static u32 low_power_update(struct dram_info *dram, u32 en) in low_power_update() argument
1512 void __iomem *pctl_base = dram->pctl; in low_power_update()
1532 static void modify_dq_deskew(struct dram_info *dram, u32 signal, u32 dir, in modify_dq_deskew() argument
1535 void __iomem *phy_base = dram->phy; in modify_dq_deskew()
1567 update_dq_rx_prebit(dram); in modify_dq_deskew()
1569 update_dq_tx_prebit(dram); in modify_dq_deskew()
1572 static int data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype) in data_training_rg() argument
1574 void __iomem *phy_base = dram->phy; in data_training_rg()
1580 void __iomem *pctl_base = dram->pctl; in data_training_rg()
1596 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_rg()
1619 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_rg()
1639 static int data_training_wl(struct dram_info *dram, u32 cs, u32 dramtype, in data_training_wl() argument
1642 void __iomem *pctl_base = dram->pctl; in data_training_wl()
1643 void __iomem *phy_base = dram->phy; in data_training_wl()
1649 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_wl()
1660 pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp | (1 << 12), in data_training_wl()
1694 pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp & ~(1 << 12), in data_training_wl()
1697 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_wl()
1709 static int data_training_rd(struct dram_info *dram, u32 cs, u32 dramtype, in data_training_rd() argument
1712 void __iomem *pctl_base = dram->pctl; in data_training_rd()
1713 void __iomem *phy_base = dram->phy; in data_training_rd()
1743 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_rd()
1811 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_rd()
1826 static int data_training_wr(struct dram_info *dram, u32 cs, u32 dramtype, in data_training_wr() argument
1829 void __iomem *pctl_base = dram->pctl; in data_training_wr()
1830 void __iomem *phy_base = dram->phy; in data_training_wr()
1845 pctl_write_mr(dram->pctl, 3, 2, 0x6, dramtype); in data_training_wr()
1848 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_wr()
1892 send_a_refresh(dram->pctl, 0x3); in data_training_wr()
1915 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_wr()
1932 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, in data_training_wr()
1939 static int data_training(struct dram_info *dram, u32 cs, in data_training() argument
1950 ret = data_training_wl(dram, cs, in data_training()
1958 ret = data_training_rg(dram, cs, in data_training()
1965 ret = data_training_rd(dram, cs, in data_training()
1973 ret = data_training_wr(dram, cs, in data_training()
1984 static int get_wrlvl_val(struct dram_info *dram, in get_wrlvl_val() argument
1988 void __iomem *phy_base = dram->phy; in get_wrlvl_val()
1992 lp_stat = low_power_update(dram, 0); in get_wrlvl_val()
1995 modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, clk_skew, 3, in get_wrlvl_val()
1998 ret = data_training(dram, 0, sdram_params, 0, WRITE_LEVELING); in get_wrlvl_val()
2000 ret |= data_training(dram, 1, sdram_params, 0, WRITE_LEVELING); in get_wrlvl_val()
2008 low_power_update(dram, lp_stat); in get_wrlvl_val()
2098 static int high_freq_training(struct dram_info *dram, in high_freq_training() argument
2103 void __iomem *phy_base = dram->phy; in high_freq_training()
2144 modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, ca_skew, 3, in high_freq_training()
2151 ret = data_training(dram, 0, sdram_params, fsp, READ_GATE_TRAINING | in high_freq_training()
2164 ret |= data_training(dram, 1, sdram_params, fsp, in high_freq_training()
2176 record_dq_prebit(dram); in high_freq_training()
2178 min_val = get_min_value(dram, SKEW_RX_SIGNAL, in high_freq_training()
2180 modify_dq_deskew(dram, SKEW_RX_SIGNAL, DESKEW_MDF_DIFF_VAL, in high_freq_training()
2188 min_val = MIN(get_min_value(dram, SKEW_TX_SIGNAL, in high_freq_training()
2190 get_min_value(dram, SKEW_CA_SIGNAL, in high_freq_training()
2194 modify_ca_deskew(dram, DESKEW_MDF_DIFF_VAL, min_val, min_val, 3, in high_freq_training()
2197 modify_dq_deskew(dram, SKEW_TX_SIGNAL, DESKEW_MDF_DIFF_VAL, in high_freq_training()
2205 ret = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING); in high_freq_training()
2207 ret |= data_training(dram, 1, sdram_params, 0, in high_freq_training()
2213 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) in set_ddrconfig() argument
2215 writel(ddrconfig, &dram->msch->deviceconf); in set_ddrconfig()
2216 clrsetbits_le32(&dram->grf->noc_con0, 0x3 << 0, 0 << 0); in set_ddrconfig()
2219 static void update_noc_timing(struct dram_info *dram, in update_noc_timing() argument
2222 void __iomem *pctl_base = dram->pctl; in update_noc_timing()
2250 &dram->msch->ddrtiminga0); in update_noc_timing()
2252 &dram->msch->ddrtimingb0); in update_noc_timing()
2254 &dram->msch->ddrtimingc0); in update_noc_timing()
2256 &dram->msch->devtodev0); in update_noc_timing()
2257 writel(sdram_params->ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); in update_noc_timing()
2259 &dram->msch->ddr4timing); in update_noc_timing()
2262 static int split_setup(struct dram_info *dram, in split_setup() argument
2297 rk_clrsetreg(&dram->ddrgrf->grf_ddrsplit_con, in split_setup()
2313 static void split_bypass(struct dram_info *dram) in split_bypass() argument
2315 if ((readl(&dram->ddrgrf->grf_ddrsplit_con) & in split_bypass()
2320 rk_clrsetreg(&dram->ddrgrf->grf_ddrsplit_con, in split_bypass()
2327 static void dram_all_config(struct dram_info *dram, in dram_all_config() argument
2332 void __iomem *pctl_base = dram->pctl; in dram_all_config()
2338 set_ddrconfig(dram, cap_info->ddrconfig); in dram_all_config()
2341 writel(sys_reg2, &dram->pmugrf->os_reg[2]); in dram_all_config()
2342 writel(sys_reg3, &dram->pmugrf->os_reg[3]); in dram_all_config()
2356 &dram->msch->devicesize); in dram_all_config()
2357 update_noc_timing(dram, sdram_params); in dram_all_config()
2360 static void enable_low_power(struct dram_info *dram, in enable_low_power() argument
2363 void __iomem *pctl_base = dram->pctl; in enable_low_power()
2366 writel(0x1f1f0617, &dram->ddrgrf->ddr_grf_con[1]); in enable_low_power()
2377 writel(grf_lp_con, &dram->ddrgrf->ddr_grf_lp_con); in enable_low_power()
2380 if (dram->pd_idle == 0) in enable_low_power()
2384 if (dram->sr_idle == 0) in enable_low_power()
2391 static void ddr_set_atags(struct dram_info *dram, in ddr_set_atags() argument
2396 void __iomem *pctl_base = dram->pctl; in ddr_set_atags()
2420 split = readl(&dram->ddrgrf->grf_ddrsplit_con); in ddr_set_atags()
2470 static int check_lp4_rzqi_value(struct dram_info *dram, u32 cs, u32 byte, u32 zq, u32 dramtype) in check_lp4_rzqi_value() argument
2474 rzqi = (read_mr(dram, BIT(cs), byte, 0, dramtype) >> 3) & 0x3; in check_lp4_rzqi_value()
2490 static int check_lp4_rzqi(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) in check_lp4_rzqi() argument
2504 if (check_lp4_rzqi_value(dram, cs, byte, byte, dramtype)) in check_lp4_rzqi()
2510 if (check_lp4_rzqi_value(dram, cs, byte, cs, dramtype)) in check_lp4_rzqi()
2567 int sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init) in sdram_init_() argument
2569 void __iomem *pctl_base = dram->pctl; in sdram_init_()
2570 void __iomem *phy_base = dram->phy; in sdram_init_()
2575 rkclk_configure_ddr(dram, sdram_params); in sdram_init_()
2577 rkclk_ddr_reset(dram, 1, 1, 1, 1); in sdram_init_()
2580 rkclk_ddr_reset(dram, 1, 1, 1, 0); in sdram_init_()
2581 phy_cfg(dram, sdram_params); in sdram_init_()
2583 rkclk_ddr_reset(dram, 1, 1, 0, 0); in sdram_init_()
2584 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 1); in sdram_init_()
2586 rkclk_ddr_reset(dram, 1, 0, 0, 0); in sdram_init_()
2587 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, in sdram_init_()
2588 dram->sr_idle, dram->pd_idle); in sdram_init_()
2613 set_ds_odt(dram, sdram_params, 0); in sdram_init_()
2615 set_ctl_address_map(dram, sdram_params); in sdram_init_()
2619 rkclk_ddr_reset(dram, 0, 0, 0, 0); in sdram_init_()
2631 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3); in sdram_init_()
2636 pctl_write_mr(dram->pctl, 3, 11, in sdram_init_()
2640 pctl_write_mr(dram->pctl, 3, 12, in sdram_init_()
2646 pctl_write_mr(dram->pctl, 3, 22, in sdram_init_()
2651 pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp | BIT(7), DDR4); in sdram_init_()
2652 pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp | BIT(7), DDR4); in sdram_init_()
2653 pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp, DDR4); in sdram_init_()
2658 tmp = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) & 0xf; in sdram_init_()
2675 mr_tmp = read_mr(dram, 1, 0, 14, LPDDR4); in sdram_init_()
2685 pctl_write_mr(dram->pctl, 3, 14, in sdram_init_()
2690 if (data_training(dram, 1, sdram_params, 0, in sdram_init_()
2699 pctl_write_vrefdq(dram->pctl, 0x3, ddr4_vref, in sdram_init_()
2703 dram_all_config(dram, sdram_params); in sdram_init_()
2704 enable_low_power(dram, sdram_params); in sdram_init_()
2709 static u64 dram_detect_cap(struct dram_info *dram, in dram_detect_cap() argument
2714 void __iomem *pctl_base = dram->pctl; in dram_detect_cap()
2715 void __iomem *phy_base = dram->phy; in dram_detect_cap()
2762 mr8 = read_mr(dram, 1, 0, 8, dram_type); in dram_detect_cap()
2788 if (data_training(dram, 1, sdram_params, 0, READ_GATE_TRAINING) == 0) in dram_detect_cap()
2797 if ((data_training_rg(dram, 0, dram_type) & 0xf) == 0) { in dram_detect_cap()
2809 if (data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) == 0) in dram_detect_cap()
2835 static int dram_detect_cs1_row(struct dram_info *dram, in dram_detect_cs1_row() argument
2840 void __iomem *pctl_base = dram->pctl; in dram_detect_cs1_row()
2904 static int sdram_init_detect(struct dram_info *dram, in sdram_init_detect() argument
2912 if (sdram_init_(dram, sdram_params, 0)) { in sdram_init_detect()
2914 if (sdram_init_(dram, sdram_params, 0)) in sdram_init_detect()
2927 split_bypass(dram); in sdram_init_detect()
2928 if (dram_detect_cap(dram, sdram_params, 0) != 0) in sdram_init_detect()
2933 ret = sdram_init_(dram, sdram_params, 1); in sdram_init_detect()
2938 dram_detect_cs1_row(dram, sdram_params, 0); in sdram_init_detect()
2940 sys_reg = readl(&dram->pmugrf->os_reg[2]); in sdram_init_detect()
2941 sys_reg3 = readl(&dram->pmugrf->os_reg[3]); in sdram_init_detect()
2944 writel(sys_reg, &dram->pmugrf->os_reg[2]); in sdram_init_detect()
2945 writel(sys_reg3, &dram->pmugrf->os_reg[3]); in sdram_init_detect()
2949 split_setup(dram, sdram_params); in sdram_init_detect()
3010 static void pre_set_rate(struct dram_info *dram, in pre_set_rate() argument
3015 void __iomem *pctl_base = dram->pctl; in pre_set_rate()
3016 void __iomem *phy_base = dram->phy; in pre_set_rate()
3021 sw_set_req(dram); in pre_set_rate()
3046 sw_set_ack(dram); in pre_set_rate()
3068 set_ds_odt(dram, sdram_params, dst_fsp); in pre_set_rate()
3073 pctl_write_mr(dram->pctl, 3, 13, in pre_set_rate()
3082 pctl_write_mr(dram->pctl, 3, 3, in pre_set_rate()
3092 pctl_write_mr(dram->pctl, 3, 1, in pre_set_rate()
3099 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, in pre_set_rate()
3107 pctl_write_mr(dram->pctl, 3, 11, in pre_set_rate()
3113 pctl_write_mr(dram->pctl, 3, 12, in pre_set_rate()
3120 pctl_write_mr(dram->pctl, 3, 22, in pre_set_rate()
3126 pctl_write_mr(dram->pctl, 3, 14, in pre_set_rate()
3133 update_noc_timing(dram, sdram_params); in pre_set_rate()
3136 static void save_fsp_param(struct dram_info *dram, u32 dst_fsp, in save_fsp_param() argument
3139 void __iomem *pctl_base = dram->pctl; in save_fsp_param()
3140 void __iomem *phy_base = dram->phy; in save_fsp_param()
3380 void ddr_set_rate(struct dram_info *dram, in ddr_set_rate() argument
3390 void __iomem *pctl_base = dram->pctl; in ddr_set_rate()
3391 void __iomem *phy_base = dram->phy; in ddr_set_rate()
3394 lp_stat = low_power_update(dram, 0); in ddr_set_rate()
3401 pre_set_rate(dram, sdram_params_new, dst_fsp, dst_fsp_lp4); in ddr_set_rate()
3429 pctl_write_mr(dram->pctl, 2, 1, cur_init3, dramtype); in ddr_set_rate()
3434 update_refresh_reg(dram); in ddr_set_rate()
3436 enter_sr(dram, 1); in ddr_set_rate()
3440 &dram->pmugrf->soc_con[0]); in ddr_set_rate()
3441 sw_set_req(dram); in ddr_set_rate()
3444 sw_set_ack(dram); in ddr_set_rate()
3446 sw_set_req(dram); in ddr_set_rate()
3456 sw_set_ack(dram); in ddr_set_rate()
3459 &dram->cru->clkgate_con[21]); in ddr_set_rate()
3466 rkclk_set_dpll(dram, freq * MHz / 2); in ddr_set_rate()
3467 phy_pll_set(dram, freq * MHz, 0); in ddr_set_rate()
3468 phy_pll_set(dram, freq * MHz, 1); in ddr_set_rate()
3473 &dram->pmugrf->soc_con[0]); in ddr_set_rate()
3475 &dram->cru->clkgate_con[21]); in ddr_set_rate()
3490 sw_set_req(dram); in ddr_set_rate()
3493 sw_set_ack(dram); in ddr_set_rate()
3494 update_refresh_reg(dram); in ddr_set_rate()
3497 enter_sr(dram, 0); in ddr_set_rate()
3504 pctl_write_mr(dram->pctl, 3, 1, in ddr_set_rate()
3508 pctl_write_mr(dram->pctl, 3, 2, dst_init3 & PCTL2_MR_MASK, in ddr_set_rate()
3510 pctl_write_mr(dram->pctl, 3, 3, in ddr_set_rate()
3514 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, dramtype); in ddr_set_rate()
3516 pctl_write_mr(dram->pctl, 3, 1, dst_init3 & PCTL2_MR_MASK, in ddr_set_rate()
3519 pctl_write_mr(dram->pctl, 3, 0, in ddr_set_rate()
3525 pctl_write_mr(dram->pctl, 3, 0, in ddr_set_rate()
3529 pctl_write_mr(dram->pctl, 3, 2, in ddr_set_rate()
3533 pctl_write_mr(dram->pctl, 3, 3, mr_tmp & PCTL2_MR_MASK, in ddr_set_rate()
3537 pctl_write_mr(dram->pctl, 3, 4, in ddr_set_rate()
3541 pctl_write_mr(dram->pctl, 3, 5, in ddr_set_rate()
3549 pctl_write_mr(dram->pctl, 3, 6, in ddr_set_rate()
3552 pctl_write_mr(dram->pctl, 3, 6, in ddr_set_rate()
3555 pctl_write_mr(dram->pctl, 3, 6, in ddr_set_rate()
3561 pctl_write_mr(dram->pctl, 3, 13, in ddr_set_rate()
3568 update_refresh_reg(dram); in ddr_set_rate()
3571 high_freq_training(dram, sdram_params_new, dst_fsp); in ddr_set_rate()
3572 low_power_update(dram, lp_stat); in ddr_set_rate()
3574 save_fsp_param(dram, dst_fsp, sdram_params_new); in ddr_set_rate()
3577 static void ddr_set_rate_for_fsp(struct dram_info *dram, in ddr_set_rate_for_fsp() argument
3606 if (get_wrlvl_val(dram, sdram_params)) in ddr_set_rate_for_fsp()