| /rk3399_rockchip-uboot/arch/x86/cpu/intel_common/ |
| H A D | me_status.c | 141 debug("ME: FW Partition Table : %s\n", in _intel_me_status()
143 debug("ME: Bringup Loader Failure : %s\n", in _intel_me_status()
145 debug("ME: Firmware Init Complete : %s\n", in _intel_me_status()
147 debug("ME: Manufacturing Mode : %s\n", in _intel_me_status()
149 debug("ME: Boot Options Present : %s\n", in _intel_me_status()
151 debug("ME: Update In Progress : %s\n", in _intel_me_status()
153 debug("ME: Current Working State : %s\n", in _intel_me_status()
155 debug("ME: Current Operation State : %s\n", in _intel_me_status()
157 debug("ME: Current Operation Mode : %s\n", in _intel_me_status()
159 debug("ME: Error Code : %s\n", in _intel_me_status()
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| /rk3399_rockchip-uboot/drivers/ddr/altera/ |
| H A D | sdram.c | 65 debug("workaround rows - memsize %lld\n", memsize); in get_errata_rows()
66 debug("workaround rows - cs %d\n", cs); in get_errata_rows()
67 debug("workaround rows - width %d\n", width); in get_errata_rows()
68 debug("workaround rows - rows %d\n", rows); in get_errata_rows()
69 debug("workaround rows - banks %d\n", banks); in get_errata_rows()
70 debug("workaround rows - cols %d\n", cols); in get_errata_rows()
73 debug("rows workaround - term1 %lld\n", newrows); in get_errata_rows()
76 debug("rows workaround - term2 %lld\n", newrows); in get_errata_rows()
85 debug("rows workaround - bits %d\n", bits); in get_errata_rows()
99 debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows); in get_errata_rows()
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| /rk3399_rockchip-uboot/drivers/ddr/fsl/ |
| H A D | mpc85xx_ddr_gen3.c | 73 debug("Workaround for ERRATUM_DDR111_DDR134\n"); in fsl_ddr_set_memctl_regs()
85 debug("Found cs%d_bns (0x%08x) covering 0xff000000, " in fsl_ddr_set_memctl_regs()
172 if (regs->debug[i]) { in fsl_ddr_set_memctl_regs()
173 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); in fsl_ddr_set_memctl_regs()
174 out_be32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
179 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
180 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
202 debug("Workaround for ERRATUM_DDR_A003\n"); in fsl_ddr_set_memctl_regs()
205 out_be32(&ddr->debug[2], 0x00000400); in fsl_ddr_set_memctl_regs()
210 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
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| /rk3399_rockchip-uboot/drivers/sound/ |
| H A D | sound-i2s.c | 40 debug("EXYNOS_SOUND: No node for sound in device tree\n"); in get_sound_i2s_values()
52 debug("%s: Missing i2s base\n", __func__); in get_sound_i2s_values()
60 debug("audio_pll_clk = %d\n", i2s->audio_pll_clk); in get_sound_i2s_values()
64 debug("samplingrate = %d\n", i2s->samplingrate); in get_sound_i2s_values()
68 debug("bitspersample = %d\n", i2s->bitspersample); in get_sound_i2s_values()
72 debug("channels = %d\n", i2s->channels); in get_sound_i2s_values()
76 debug("rfs = %d\n", i2s->rfs); in get_sound_i2s_values()
80 debug("bfs = %d\n", i2s->bfs); in get_sound_i2s_values()
84 debug("id = %d\n", i2s->id); in get_sound_i2s_values()
87 debug("fail to get sound i2s node properties\n"); in get_sound_i2s_values()
[all …]
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| H A D | max98095.c | 56 debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n", in max98095_i2c_write()
75 debug("%s: Error while reading register %#04x\n", in max98095_i2c_read()
172 debug("%s: Illegal bits per sample %d.\n", in max98095_hw_params()
178 debug("%s: Failed to set sample rate to %d.\n", in max98095_hw_params()
196 debug("%s: Error setting hardware params.\n", __func__); in max98095_hw_params()
232 debug("%s: Invalid master clock frequency\n", __func__); in max98095_set_sysclk()
236 debug("%s: Clock at %uHz\n", __func__, freq); in max98095_set_sysclk()
296 debug("%s: Clock mode unsupported\n", __func__); in max98095_set_fmt()
307 debug("%s: Unrecognized format.\n", __func__); in max98095_set_fmt()
324 debug("%s: Unrecognized inversion settings.\n", __func__); in max98095_set_fmt()
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| H A D | wm8994.c | 92 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data); in wm8994_i2c_write()
112 debug("%s: Error while reading register %#04x\n", in wm8994_i2c_read()
181 debug("%s: Invalid audio interface selection\n", __func__); in wm8994_set_fmt()
192 debug("%s: Invalid i2s master selection\n", __func__); in wm8994_set_fmt()
211 debug("%s: Invalid i2s format selection\n", __func__); in wm8994_set_fmt()
226 debug("%s: Invalid i2s frame inverse selection\n", in wm8994_set_fmt()
248 debug("%s: Invalid i2s clock polarity selection\n", in wm8994_set_fmt()
254 debug("%s: Invalid i2s format selection\n", __func__); in wm8994_set_fmt()
265 debug("%s: codec register access error\n", __func__); in wm8994_set_fmt()
344 debug("%s: Could not get the best matching samplingrate\n", in wm8994_hw_params()
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/ |
| H A D | cpu.c | 26 debug("%s entry\n", __func__); in enable_cpu_power_rail()
51 debug("%s entry\n", __func__); in enable_cpu_clocks()
56 debug("%s: PLLX base = 0x%08X\n", __func__, reg); in enable_cpu_clocks()
59 debug("%s: PLLX locked, delay for stable clocks\n", __func__); in enable_cpu_clocks()
63 debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__); in enable_cpu_clocks()
67 debug("%s: Enabling clock to all CPUs\n", __func__); in enable_cpu_clocks()
73 debug("%s: Enabling main CPU complex clocks\n", __func__); in enable_cpu_clocks()
79 debug("%s: Done\n", __func__); in enable_cpu_clocks()
87 debug("%s entry\n", __func__); in remove_cpu_resets()
120 debug("%s entry\n", __func__); in tegra124_init_clocks()
[all …]
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| /rk3399_rockchip-uboot/common/ |
| H A D | usb_hub.c | 171 debug("enabling power on all ports\n"); in usb_hub_power_on()
174 debug("port %d returns %lX\n", i + 1, dev->status); in usb_hub_power_on()
196 debug("pgood_delay=%dms\n", pgood_delay); in usb_hub_power_on()
210 debug("devnum=%d poweron: query_delay=%d connect_timeout=%d\n", in usb_hub_power_on()
280 debug("%s: resetting '%s' port %d...\n", __func__, dev->dev->name, in usb_hub_port_reset()
283 debug("%s: resetting port %d...\n", __func__, port + 1); in usb_hub_port_reset()
293 debug("get_port_status failed status %lX\n", in usb_hub_port_reset()
300 debug("portstatus %x, change %x, %s\n", portstatus, portchange, in usb_hub_port_reset()
303 debug("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \ in usb_hub_port_reset()
334 debug("Cannot enable port %i after %i retries, " \ in usb_hub_port_reset()
[all …]
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| H A D | usb_storage.c | 131 debug("."); in usb_show_progress()
183 debug("Get Max LUN -> len = %i, result = %i\n", len, (int) *result); in usb_get_max_lun()
201 debug("\n\nProbing for storage\n"); in usb_stor_probe_device()
222 debug("Cannot bind driver\n"); in usb_stor_probe_device()
235 debug("%s: Found device %p\n", __func__, udev); in usb_stor_probe_device()
237 debug("usb_stor_get_info: Invalid device\n"); in usb_stor_probe_device()
279 debug("partype: %d\n", blkdev->part_type); in usb_stor_probe_device()
281 debug("partype: %d\n", blkdev->part_type); in usb_stor_probe_device()
283 debug("%s: Found device %p\n", __func__, udev); in usb_stor_probe_device()
316 debug("i=%d\n", i); in usb_stor_scan()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-uniphier/debug-uart/ |
| H A D | Makefile | 6 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o
8 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += debug-uart-pro5.o
10 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += debug-uart-pxs2.o
11 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += debug-uart-ld6b.o
12 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += debug-uart-ld20.o
13 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += debug-uart-ld20.o
16 obj-y += debug-uart.o
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| /rk3399_rockchip-uboot/drivers/usb/gadget/ |
| H A D | rndis.c | 169 debug("query OID %08x value, len %d:\n", OID, buf_len); in gen_ndis_query_resp()
171 debug("%03d: %08x %08x %08x %08x\n", i, in gen_ndis_query_resp()
191 debug("%s: OID_GEN_SUPPORTED_LIST\n", __func__); in gen_ndis_query_resp()
201 debug("%s: OID_GEN_HARDWARE_STATUS\n", __func__); in gen_ndis_query_resp()
215 debug("%s: OID_GEN_MEDIA_SUPPORTED\n", __func__); in gen_ndis_query_resp()
222 debug("%s: OID_GEN_MEDIA_IN_USE\n", __func__); in gen_ndis_query_resp()
230 debug("%s: OID_GEN_MAXIMUM_FRAME_SIZE\n", __func__); in gen_ndis_query_resp()
240 debug("%s: OID_GEN_LINK_SPEED\n", __func__); in gen_ndis_query_resp()
251 debug("%s: OID_GEN_TRANSMIT_BLOCK_SIZE\n", __func__); in gen_ndis_query_resp()
260 debug("%s: OID_GEN_RECEIVE_BLOCK_SIZE\n", __func__); in gen_ndis_query_resp()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/ |
| H A D | spl_resource_img.c | 16 debug("bad resource image magic: %s\n", in spl_resource_image_check_header()
21 debug("resource image header:\n"); in spl_resource_image_check_header()
22 debug("magic:%s\n", hdr->magic); in spl_resource_image_check_header()
23 debug("version:%d\n", hdr->version); in spl_resource_image_check_header()
24 debug("c_version:%d\n", hdr->c_version); in spl_resource_image_check_header()
25 debug("blks:%d\n", hdr->blks); in spl_resource_image_check_header()
26 debug("c_offset:%d\n", hdr->c_offset); in spl_resource_image_check_header()
27 debug("e_blks:%d\n", hdr->e_blks); in spl_resource_image_check_header()
28 debug("e_num:%d\n", hdr->e_nums); in spl_resource_image_check_header()
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| /rk3399_rockchip-uboot/arch/x86/lib/ |
| H A D | spl.c | 34 debug("%s starting\n", __func__); in x86_spl_init()
37 debug("%s: spl_init() failed\n", __func__); in x86_spl_init()
42 debug("%s: arch_cpu_init() failed\n", __func__); in x86_spl_init()
47 debug("%s: arch_cpu_init_dm() failed\n", __func__); in x86_spl_init()
53 debug("%s: print_cpuinfo() failed\n", __func__); in x86_spl_init()
58 debug("%s: dram_init() failed\n", __func__); in x86_spl_init()
66 debug("%s: interrupt_init() failed\n", __func__); in x86_spl_init()
85 debug("%s: SPI cache setup failed\n", __func__); in x86_spl_init()
98 debug("Error %d\n", ret); in board_init_f()
110 debug("cache status %d\n", dcache_status()); in board_init_f_r()
[all …]
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| /rk3399_rockchip-uboot/drivers/video/exynos/ |
| H A D | exynos_mipi_dsi_common.c | 68 debug("count = 3 payload = %x, %x %x %x\n", in exynos_mipi_dsi_long_data_wr()
75 debug("count = 2 payload = %x, %x %x\n", payload, in exynos_mipi_dsi_long_data_wr()
87 debug("count = 4 payload = %x, %x %x %x %x\n", in exynos_mipi_dsi_long_data_wr()
105 debug("state is ULPS.\n"); in exynos_mipi_dsi_wr_data()
122 debug("SRF header fifo is not empty.\n"); in exynos_mipi_dsi_wr_data()
136 debug("data0 = %x data1 = %x\n", in exynos_mipi_dsi_wr_data()
194 debug("count = %d payload = %x,%x %x %x\n", in exynos_mipi_dsi_wr_data()
225 debug("data id %x is not supported current DSI spec.\n", in exynos_mipi_dsi_wr_data()
286 debug("fin_pll range should be 6MHz ~ 12MHz\n"); in exynos_mipi_dsi_change_pll()
304 debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n", in exynos_mipi_dsi_change_pll()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-kirkwood/ |
| H A D | mpp.c | 26 debug("MPP setup: unknown kirkwood variant\n"); in kirkwood_variant()
44 debug( "initial MPP regs:"); in kirkwood_mpp_conf()
47 debug(" %08x", mpp_ctrl[i]); in kirkwood_mpp_conf()
49 debug("\n"); in kirkwood_mpp_conf()
59 debug("kirkwood_mpp_conf: invalid MPP " in kirkwood_mpp_conf()
64 debug("kirkwood_mpp_conf: requested MPP%u config " in kirkwood_mpp_conf()
83 debug(" final MPP regs:"); in kirkwood_mpp_conf()
86 debug(" %08x", mpp_ctrl[i]); in kirkwood_mpp_conf()
88 debug("\n"); in kirkwood_mpp_conf()
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| /rk3399_rockchip-uboot/arch/x86/lib/fsp/ |
| H A D | fsp_common.c | 40 debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); in fsp_init_phase_pci()
43 debug("fail, error code %x\n", status); in fsp_init_phase_pci()
45 debug("OK\n"); in fsp_init_phase_pci()
77 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); in board_final_cleanup()
80 debug("fail, error code %x\n", status); in board_final_cleanup()
82 debug("OK\n"); in board_final_cleanup()
101 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, in fsp_prepare_mrc_cache()
118 debug("Cannot find RTC: err=%d\n", ret); in fsp_save_s3_stack()
125 debug("Save stack address to CMOS: err=%d\n", ret); in fsp_save_s3_stack()
154 debug("No MRC cache found in S3 resume path\n"); in arch_fsp_init()
[all …]
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| /rk3399_rockchip-uboot/drivers/bios_emulator/include/x86emu/ |
| H A D | debug.h | 64 # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F)
65 # define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F)
66 # define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F)
67 # define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F)
68 # define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F)
69 # define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F)
70 # define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F)
71 # define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP)
73 # define DEBUG_FS() (M.x86.debug & DEBUG_FS_F)
74 # define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F)
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| /rk3399_rockchip-uboot/arch/x86/cpu/ivybridge/ |
| H A D | sdram.c | 64 debug("Cannot find RTC: err=%d\n", ret); in read_seed_from_cmos()
80 debug("Failed to read from RTC %s\n", dev->name); in read_seed_from_cmos()
84 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", in read_seed_from_cmos()
86 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", in read_seed_from_cmos()
100 debug("%s: invalid seed checksum\n", __func__); in read_seed_from_cmos()
127 debug("%s: at %p, size %x checksum %04x\n", __func__, in prepare_mrc_cache()
142 debug("Cannot find RTC: err=%d\n", ret); in write_seeds_to_cmos()
148 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", in write_seeds_to_cmos()
152 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", in write_seeds_to_cmos()
213 debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret); in copy_spd()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 115 debug("Starting write leveling calibration.\n"); in mmdc_do_write_level_calibration()
161 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors); in mmdc_do_write_level_calibration()
169 …debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. … in mmdc_do_write_level_calibration()
194 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
196 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
199 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
201 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
333 debug("Starting Read DQS Gating calibration.\n"); in mmdc_do_dqs_calibration()
395 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
402 debug("Starting Read Delay calibration.\n"); in mmdc_do_dqs_calibration()
[all …]
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| /rk3399_rockchip-uboot/board/broadcom/bcmstb/ |
| H A D | bcmstb.c | 139 debug("BCMSTB SDHCI base address: 0x%p\n", (void *)sdhci_base_address); in board_mmc_init()
168 debug("Arguments from prior stage bootloader:\n"); in board_late_init()
169 debug("General Purpose Register 0: 0x%x\n", bcmstb_boot_parameters.r0); in board_late_init()
170 debug("General Purpose Register 1: 0x%x\n", bcmstb_boot_parameters.r1); in board_late_init()
171 debug("General Purpose Register 2: 0x%x\n", bcmstb_boot_parameters.r2); in board_late_init()
172 debug("General Purpose Register 3: 0x%x\n", bcmstb_boot_parameters.r3); in board_late_init()
173 debug("Stack Pointer Register: 0x%x\n", bcmstb_boot_parameters.sp); in board_late_init()
174 debug("Link Register: 0x%x\n", bcmstb_boot_parameters.lr); in board_late_init()
175 debug("Assuming timer frequency register at: 0x%p\n", in board_late_init()
177 debug("Read timer frequency (in Hz): %ld\n", gd->arch.timer_rate_hz); in board_late_init()
[all …]
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| /rk3399_rockchip-uboot/drivers/remoteproc/ |
| H A D | sandbox_testproc.c | 81 debug("current_state=%d, next_state=%d\n", ddata->current_state, in sandbox_dev_move_to_state()
132 debug("%s: platform private data missing\n", uc_pdata->name); in sandbox_testproc_probe()
136 debug("%s: called(%d)\n", uc_pdata->name, ret); in sandbox_testproc_probe()
156 debug("%s: called(%d)\n", uc_pdata->name, ret); in sandbox_testproc_init()
158 debug("%s init failed\n", uc_pdata->name); in sandbox_testproc_init()
178 debug("%s: called(%d)\n", uc_pdata->name, ret); in sandbox_testproc_reset()
181 debug("%s reset failed\n", uc_pdata->name); in sandbox_testproc_reset()
202 debug("%s: called(%d) Loading to %08lX %lu size\n", in sandbox_testproc_load()
206 debug("%s load failed\n", uc_pdata->name); in sandbox_testproc_load()
225 debug("%s: called(%d)\n", uc_pdata->name, ret); in sandbox_testproc_start()
[all …]
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| /rk3399_rockchip-uboot/drivers/reset/ |
| H A D | reset-uclass.c | 23 debug("%s(reset_ctl=%p)\n", __func__, reset_ctl); in reset_of_xlate_default()
26 debug("Invaild args_count: %d\n", args->args_count); in reset_of_xlate_default()
43 debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index, in reset_get_by_index()
50 debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n", in reset_get_by_index()
58 debug("%s: uclass_get_device_by_ofnode() failed: %d\n", in reset_get_by_index()
60 debug("%s %d\n", ofnode_get_name(args.node), args.args[0]); in reset_get_by_index()
71 debug("of_xlate() failed: %d\n", ret); in reset_get_by_index()
77 debug("ops->request() failed: %d\n", ret); in reset_get_by_index()
112 debug("%s: could release all resets for %p\n", in reset_get_bulk()
123 debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name, in reset_get_by_name()
[all …]
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| /rk3399_rockchip-uboot/drivers/mailbox/ |
| H A D | mailbox-uclass.c | 22 debug("%s(chan=%p)\n", __func__, chan); in mbox_of_xlate_default()
25 debug("Invaild args_count: %d\n", args->args_count); in mbox_of_xlate_default()
41 debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan); in mbox_get_by_index()
46 debug("%s: dev_read_phandle_with_args failed: %d\n", __func__, in mbox_get_by_index()
53 debug("%s: uclass_get_device_by_of_offset failed: %d\n", in mbox_get_by_index()
65 debug("of_xlate() failed: %d\n", ret); in mbox_get_by_index()
71 debug("ops->request() failed: %d\n", ret); in mbox_get_by_index()
83 debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan); in mbox_get_by_name()
87 debug("fdt_stringlist_search() failed: %d\n", index); in mbox_get_by_name()
98 debug("%s(chan=%p)\n", __func__, chan); in mbox_free()
[all …]
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| /rk3399_rockchip-uboot/lib/ |
| H A D | fdtdec_common.c | 19 #define debug(...) macro
28 debug("%s: %s: ", __func__, prop_name); in fdtdec_get_int()
33 debug("%#x (%d)\n", val, val); in fdtdec_get_int()
36 debug("(not found)\n"); in fdtdec_get_int()
46 debug("%s: %s: ", __func__, prop_name); in fdtdec_get_uint()
51 debug("%#x (%d)\n", val, val); in fdtdec_get_uint()
54 debug("(not found)\n"); in fdtdec_get_uint()
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| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/ |
| H A D | spd_sdram.c | 169 debug("DDR: Module mem type is %02X\n", spd.mem_type); in spd_sdram()
227 debug("\n"); in spd_sdram()
228 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); in spd_sdram()
229 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); in spd_sdram()
240 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); in spd_sdram()
241 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); in spd_sdram()
252 debug("\n"); in spd_sdram()
253 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); in spd_sdram()
254 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); in spd_sdram()
265 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); in spd_sdram()
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