169 		debug("DDR: Module mem type is %02X\n", spd.mem_type);  in spd_sdram()
227 	debug("\n");  in spd_sdram()
228 	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);  in spd_sdram()
229 	debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);  in spd_sdram()
240 		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);  in spd_sdram()
241 		debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);  in spd_sdram()
252 	debug("\n");  in spd_sdram()
253 	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);  in spd_sdram()
254 	debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);  in spd_sdram()
265 		debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);  in spd_sdram()
266 		debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);  in spd_sdram()
285 	debug("DDR:bar=0x%08x\n", ecm->bar);  in spd_sdram()
286 	debug("DDR:ar=0x%08x\n", ecm->ar);  in spd_sdram()
317 	debug("DDR: caslat SPD bit is %d\n", caslat);  in spd_sdram()
323 	debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);  in spd_sdram()
423 	debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);  in spd_sdram()
424 	debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);  in spd_sdram()
440 		debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);  in spd_sdram()
453 	debug("DDR: effective data rate is %d MHz\n", effective_data_rate);  in spd_sdram()
454 	debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",  in spd_sdram()
473 		debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);  in spd_sdram()
632 	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);  in spd_sdram()
633 	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);  in spd_sdram()
641 		debug("\n   DDR DIMM: data bus width is 32 bit");  in spd_sdram()
644 		debug("\n   DDR DIMM: data bus width is 64 bit");  in spd_sdram()
649 		debug(" with ECC\n");  in spd_sdram()
651 		debug(" without ECC\n");  in spd_sdram()
698 	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);  in spd_sdram()
704 	debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);  in spd_sdram()
741 	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);  in spd_sdram()
759 		debug("DDR: sdram_cfg2  = 0x%08x\n", ddr->sdram_cfg2);  in spd_sdram()
765 	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);  in spd_sdram()
823 	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);  in spd_sdram()
824 	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);  in spd_sdram()
826 	debug("   DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");  in spd_sdram()
839 	debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);  in spd_sdram()
894 	debug("ddr init: CPU FP write method\n");  in ddr_enable_ecc()
905 	debug("\nREADY!!\n");  in ddr_enable_ecc()
906 	debug("ddr init duration: %ld ms\n", t_end - t_start);  in ddr_enable_ecc()