68 			debug("count = 3 payload = %x, %x %x %x\n",  in exynos_mipi_dsi_long_data_wr()
75 			debug("count = 2 payload = %x, %x %x\n", payload,  in exynos_mipi_dsi_long_data_wr()
87 			debug("count = 4 payload = %x, %x %x %x %x\n",  in exynos_mipi_dsi_long_data_wr()
105 		debug("state is ULPS.\n");  in exynos_mipi_dsi_wr_data()
122 				debug("SRF header fifo is not empty.\n");  in exynos_mipi_dsi_wr_data()
136 		debug("data0 = %x data1 = %x\n",  in exynos_mipi_dsi_wr_data()
194 			debug("count = %d payload = %x,%x %x %x\n",  in exynos_mipi_dsi_wr_data()
225 		debug("data id %x is not supported current DSI spec.\n",  in exynos_mipi_dsi_wr_data()
286 		debug("fin_pll range should be 6MHz ~ 12MHz\n");  in exynos_mipi_dsi_change_pll()
304 	debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",  in exynos_mipi_dsi_change_pll()
307 		debug("fvco range should be 500MHz ~ 1000MHz\n");  in exynos_mipi_dsi_change_pll()
310 	debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",  in exynos_mipi_dsi_change_pll()
320 	debug("freq_band = %d\n", freq_band);  in exynos_mipi_dsi_change_pll()
335 	debug("FOUT of mipi dphy pll is %luMHz\n",  in exynos_mipi_dsi_change_pll()
360 				debug("failed to get hs clock.\n");  in exynos_mipi_dsi_set_clock()
369 			debug("not support EXT CLK source for MIPI DSIM\n");  in exynos_mipi_dsi_set_clock()
371 			debug("not support EXT CLK source for MIPI DSIM\n");  in exynos_mipi_dsi_set_clock()
375 		debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",  in exynos_mipi_dsi_set_clock()
382 		debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",  in exynos_mipi_dsi_set_clock()
394 		debug("byte clock is %luMHz\n",  in exynos_mipi_dsi_set_clock()
396 		debug("escape clock that user's need is %lu\n",  in exynos_mipi_dsi_set_clock()
398 		debug("escape clock divider is %x\n", esc_div);  in exynos_mipi_dsi_set_clock()
399 		debug("escape clock is %luMHz\n",  in exynos_mipi_dsi_set_clock()
405 			debug("error rate is %lu over.\n",  in exynos_mipi_dsi_set_clock()
410 			debug("error rate is %lu under.\n",  in exynos_mipi_dsi_set_clock()
448 		debug("data lane is invalid.\n");  in exynos_mipi_dsi_init_dsim()
513 	debug("lcd panel ==> width = %d, height = %d\n",  in exynos_mipi_dsi_set_display_mode()
540 				debug("DSI Master is not stop state.\n");  in exynos_mipi_dsi_init_link()
541 				debug("Check initialization process\n");  in exynos_mipi_dsi_init_link()
559 		debug("DSI Master is already init.\n");  in exynos_mipi_dsi_init_link()
580 			debug("clock source is external bypass.\n");  in exynos_mipi_dsi_set_hs_enable()
582 		debug("DSIM is not stop state.\n");  in exynos_mipi_dsi_set_hs_enable()
592 			debug("HS Clock lane is not enabled.\n");  in exynos_mipi_dsi_set_data_transfer_mode()
600 			debug("DSI Master is not STOP or HSDT state.\n");  in exynos_mipi_dsi_set_data_transfer_mode()