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/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dmp.c78 u32 cores, cpu_up_mask = 1; in fsl_layerscape_wake_seconday_cores() local
89 cores = cpu_mask(); in fsl_layerscape_wake_seconday_cores()
109 rst->brrl = cores; in fsl_layerscape_wake_seconday_cores()
141 gur_out32(&gur->brrl, cores); in fsl_layerscape_wake_seconday_cores()
145 scfg_out32(&scfg->corebcr, cores); in fsl_layerscape_wake_seconday_cores()
163 if (hweight32(cpu_up_mask) == hweight32(cores)) in fsl_layerscape_wake_seconday_cores()
169 cores, cpu_up_mask); in fsl_layerscape_wake_seconday_cores()
172 printf("All (%d) cores are up.\n", hweight32(cores)); in fsl_layerscape_wake_seconday_cores()
211 u32 cores = cpu_pos_mask(); in core_to_pos() local
216 } else if (nr >= hweight32(cores)) { in core_to_pos()
/rk3399_rockchip-uboot/doc/
H A DREADME.mpc85xx-spin-table6 __secondary_start_page. For other cores to use the spin table, the booting
12 page translation for secondary cores to use this page of memory. Then 4KB
17 that secondary cores can see it.
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
H A DREADME.Heterogeneous-SoCs5 configuration and frequencies of all PowerPC cores and devices
7 SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
19 Code added in this file to print the DSP cores and other device's(CPRI,
25 required cores and devices from RCW and System frequency
29 Added API to get the number of SC cores in running system and Their BIT
44 Global structure updated for dsp cores and other components
73 DSP cores and other device's components have been added in this structure.
H A DREADME.srio-pcie-boot-corenet22 the boot location to SRIO or PCIE, and holdoff all the cores.
37 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
44 2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
70 h) Since all cores of slave in holdoff, slave should be powered on before
85 1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
H A DREADME.b4860qds8 StarCore and Power Architecture® cores. It targets the broadband wireless
28 e6500 cores, SC3900 FVP cores, memories and external interfaces.
37 management, and allocation tasks from the cores
108 1. Less e6500 cores: 1 cluster with 2 e6500 cores
109 2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
H A DREADME.socfpga28 projects must have the IP cores updated as shown below.
42 Then (if necessary) update the IP cores in the project, generate HDL code, and
46 $ qsys-generate soc_system.qsys --upgrade-ip-cores
H A DREADME.ARC5 More information on ARC cores avaialble here:
H A DREADME.NDS3236 Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
H A DREADME.xtensa9 SoC cores in the same manner as ARM, MIPS, etc.
11 Xtensa licensees create their own Xtensa cores with selected features
H A DREADME.spear14 1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux)
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/
H A DKconfig43 cores, count the reserved ports. This will allocate enough memory
44 in spin table to properly handle all cores.
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsocfpga_cyclone5.dtsi8 /* First 4KB has trampoline code for secondary cores. */
H A Dsocfpga_arria5.dtsi8 /* First 4KB has trampoline code for secondary cores. */
H A Dimx6dl.dtsi110 cores = <&gpu_2d>, <&gpu_3d>;
H A Dsun9i-a80-cx-a99.dts118 * OZ80120 voltage regulator for the four Cortex-A15 CPU cores.
120 * range for the CPU cores is only 800 - 1100 mV.
H A Dimx6q.dtsi208 cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A DKconfig7 bool "Enable data coherency with other cores in cluster"
12 For A53, it enables data coherency with other cores in the
15 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
129 of CPU cores, platforms with asymmetric clusters don't apply here.
/rk3399_rockchip-uboot/arch/arc/
H A DKconfig18 The original ARC ISA of ARC600/700 cores
23 ISA for the Next Generation ARC-HS cores
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 processor cores with datapath acceleration optimized for L2/3 packet
51 processor cores with high-performance data path acceleration logic and network
137 processor cores with datapath acceleration optimized for L2/3 packet
178 processor cores with high-performance data path acceleration logic and network
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3368/
H A DKconfig14 - 8x Cortex-A53 (in 2 clusters of 4 cores each)
/rk3399_rockchip-uboot/board/freescale/ls1021aqds/
H A DREADME14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
/rk3399_rockchip-uboot/board/freescale/ls1021atwr/
H A DREADME14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
/rk3399_rockchip-uboot/board/freescale/t1040qds/
H A DREADME9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
/rk3399_rockchip-uboot/board/freescale/t208xqds/
H A DREADME7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
52 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
/rk3399_rockchip-uboot/board/freescale/p2041rdb/
H A DREADME3 The P2041 Processor combines four Power Architecture processor cores

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