| #
a187559e |
| 06-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed
Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
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| #
ffd06e02 |
| 08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set fo
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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