xref: /rk3399_rockchip-uboot/arch/arm/dts/socfpga_arria5.dtsi (revision 2a8696dfc2c6547c41836ceda573ad4548cba357)

/*
 *  Copyright (C) 2013 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/dts-v1/;
/* First 4KB has trampoline code for secondary cores. */
/memreserve/ 0x00000000 0x0001000;
#include "socfpga.dtsi"

/ {
	soc {
		clkmgr@ffd04000 {
			clocks {
				osc1 {
					clock-frequency = <25000000>;
				};
			};
		};

		mmc0: dwmmc0@ff704000 {
			num-slots = <1>;
			broken-cd;
			bus-width = <4>;
			cap-mmc-highspeed;
			cap-sd-highspeed;
			drvsel = <3>;
			smplsel = <0>;
		};

		sysmgr@ffd08000 {
			cpu1-start-addr = <0xffd080c4>;
		};
	};
};