xref: /rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/Kconfig (revision 6500ec7a5a2a2a59128dba6f49d9905fc1258811)
10a37cf8fSYork Sunconfig ARCH_LS1021A
24a444176SYork Sun	bool
3ba1b6fb5SYork Sun	select SYS_FSL_ERRATUM_A008378
4ba1b6fb5SYork Sun	select SYS_FSL_ERRATUM_A008407
5ba1b6fb5SYork Sun	select SYS_FSL_ERRATUM_A009663
6ba1b6fb5SYork Sun	select SYS_FSL_ERRATUM_A009942
70a37cf8fSYork Sun	select SYS_FSL_ERRATUM_A010315
8f534b8f5SYork Sun	select SYS_FSL_SRDS_1
9f534b8f5SYork Sun	select SYS_HAS_SERDES
10d26e34c4SYork Sun	select SYS_FSL_DDR_BE if SYS_FSL_DDR
11d26e34c4SYork Sun	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
12d26e34c4SYork Sun	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
13d26e34c4SYork Sun	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
142c2e2c9eSYork Sun	select SYS_FSL_HAS_SEC
152c2e2c9eSYork Sun	select SYS_FSL_SEC_COMPAT_5
1690b80386SYork Sun	select SYS_FSL_SEC_LE
17fedb428cSSimon Glass	imply SCSI
18*6500ec7aSSimon Glass	imply CMD_PCI
195e8bd7e1SYork Sun
20fb2bf8c2SYork Sunmenu "LS102xA architecture"
21fb2bf8c2SYork Sun	depends on ARCH_LS1021A
22fb2bf8c2SYork Sun
2319538f30SHou Zhiqiangconfig FSL_PCIE_COMPAT
2419538f30SHou Zhiqiang	string "PCIe compatible of Kernel DT"
2519538f30SHou Zhiqiang	depends on PCIE_LAYERSCAPE
2619538f30SHou Zhiqiang	default "fsl,ls1021a-pcie" if ARCH_LS1021A
2719538f30SHou Zhiqiang	help
2819538f30SHou Zhiqiang	  This compatible is used to find pci controller node in Kernel DT
2919538f30SHou Zhiqiang	  to complete fixup.
3019538f30SHou Zhiqiang
315e8bd7e1SYork Sunconfig LS1_DEEP_SLEEP
324a444176SYork Sun	bool "Deep sleep"
334a444176SYork Sun	depends on ARCH_LS1021A
34fb2bf8c2SYork Sun
35b4b60d06SYork Sunconfig MAX_CPUS
36b4b60d06SYork Sun	int "Maximum number of CPUs permitted for LS102xA"
37b4b60d06SYork Sun	depends on ARCH_LS1021A
38b4b60d06SYork Sun	default 2
39b4b60d06SYork Sun	help
40b4b60d06SYork Sun	  Set this number to the maximum number of possible CPUs in the SoC.
41b4b60d06SYork Sun	  SoCs may have multiple clusters with each cluster may have multiple
42b4b60d06SYork Sun	  ports. If some ports are reserved but higher ports are used for
43b4b60d06SYork Sun	  cores, count the reserved ports. This will allocate enough memory
44b4b60d06SYork Sun	  in spin table to properly handle all cores.
45b4b60d06SYork Sun
4672ccd31eSYork Sunconfig SECURE_BOOT
4772ccd31eSYork Sun	bool	"Secure Boot"
4872ccd31eSYork Sun	help
4972ccd31eSYork Sun		Enable Freescale Secure Boot feature. Normally selected
5072ccd31eSYork Sun		by defconfig. If unsure, do not change.
5172ccd31eSYork Sun
52fb2bf8c2SYork Sunconfig SYS_FSL_ERRATUM_A010315
53fb2bf8c2SYork Sun	bool "Workaround for PCIe erratum A010315"
54fb2bf8c2SYork Sun
55f534b8f5SYork Sunconfig SYS_FSL_SRDS_1
56f534b8f5SYork Sun	bool
57f534b8f5SYork Sun
58f534b8f5SYork Sunconfig SYS_FSL_SRDS_2
59f534b8f5SYork Sun	bool
60f534b8f5SYork Sun
61f534b8f5SYork Sunconfig SYS_HAS_SERDES
62f534b8f5SYork Sun	bool
63f534b8f5SYork Sun
6425af7dc1SYork Sunconfig SYS_FSL_IFC_BANK_COUNT
6525af7dc1SYork Sun	int "Maximum banks of Integrated flash controller"
6625af7dc1SYork Sun	depends on ARCH_LS1021A
6725af7dc1SYork Sun	default 8
6825af7dc1SYork Sun
69ba1b6fb5SYork Sunconfig SYS_FSL_ERRATUM_A008407
70ba1b6fb5SYork Sun	bool
71ba1b6fb5SYork Sun
72fb2bf8c2SYork Sunendmenu
73