151c580c6SStefan Roese/* 251c580c6SStefan Roese * Copyright (C) 2012 Altera Corporation <www.altera.com> 351c580c6SStefan Roese * 45bf1f1edSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 551c580c6SStefan Roese */ 651c580c6SStefan Roese 751c580c6SStefan Roese/dts-v1/; 851c580c6SStefan Roese/* First 4KB has trampoline code for secondary cores. */ 951c580c6SStefan Roese/memreserve/ 0x00000000 0x0001000; 1051c580c6SStefan Roese#include "socfpga.dtsi" 1151c580c6SStefan Roese 1251c580c6SStefan Roese/ { 1351c580c6SStefan Roese soc { 1451c580c6SStefan Roese clkmgr@ffd04000 { 1551c580c6SStefan Roese clocks { 1651c580c6SStefan Roese osc1 { 1751c580c6SStefan Roese clock-frequency = <25000000>; 1851c580c6SStefan Roese }; 1951c580c6SStefan Roese }; 2051c580c6SStefan Roese }; 2151c580c6SStefan Roese 2251c580c6SStefan Roese mmc0: dwmmc0@ff704000 { 2351c580c6SStefan Roese num-slots = <1>; 2451c580c6SStefan Roese broken-cd; 2551c580c6SStefan Roese bus-width = <4>; 2651c580c6SStefan Roese cap-mmc-highspeed; 2751c580c6SStefan Roese cap-sd-highspeed; 28*271e9ecdSChin Liang See drvsel = <3>; 29*271e9ecdSChin Liang See smplsel = <0>; 3051c580c6SStefan Roese }; 3151c580c6SStefan Roese 3251c580c6SStefan Roese sysmgr@ffd08000 { 3351c580c6SStefan Roese cpu1-start-addr = <0xffd080c4>; 3451c580c6SStefan Roese }; 3551c580c6SStefan Roese }; 3651c580c6SStefan Roese}; 37