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Searched refs:GPIO_BASE (Results 1 – 21 of 21) sorted by relevance

/rk3399_rockchip-uboot/drivers/gpio/
H A Dkona_gpio.c11 #define GPIO_BASE (void *)GPIO2_BASE_ADDR macro
50 writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); in gpio_request()
52 value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio); in gpio_request()
53 writel(value, GPIO_BASE + off); in gpio_request()
62 writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); in gpio_free()
64 value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio); in gpio_free()
65 writel(value, GPIO_BASE + off); in gpio_free()
74 val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); in gpio_direction_input()
77 writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); in gpio_direction_input()
88 val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); in gpio_direction_output()
[all …]
H A Dlpc32xx_gpio.c307 gpio_priv->regs = (struct gpio_regs *)GPIO_BASE; in lpc32xx_gpio_probe()
/rk3399_rockchip-uboot/board/renesas/sh7785lcr/
H A Dlowlevel_init.S189 #define GPIO_BASE 0xffe70000 macro
190 PACR_A: .long GPIO_BASE + 0x00
191 PBCR_A: .long GPIO_BASE + 0x02
192 PCCR_A: .long GPIO_BASE + 0x04
193 PDCR_A: .long GPIO_BASE + 0x06
194 PECR_A: .long GPIO_BASE + 0x08
195 PFCR_A: .long GPIO_BASE + 0x0a
196 PGCR_A: .long GPIO_BASE + 0x0c
197 PHCR_A: .long GPIO_BASE + 0x0e
198 PJCR_A: .long GPIO_BASE + 0x10
[all …]
/rk3399_rockchip-uboot/drivers/pch/
H A Dpch9.c11 #define GPIO_BASE 0x48 macro
39 dm_pci_read_config32(dev, GPIO_BASE, &base); in pch9_get_gpio_base()
H A Dpch7.c11 #define GPIO_BASE 0x44 macro
55 dm_pci_read_config32(dev, GPIO_BASE, &base); in pch7_get_gpio_base()
/rk3399_rockchip-uboot/arch/arm/cpu/arm920t/ep93xx/
H A Dled.c18 register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; in switch_LED_on()
26 register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; in switch_LED_off()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h29 #define GPIO_BASE 0x40028000 /* GPIO registers base */ macro
/rk3399_rockchip-uboot/board/timll/devkit3250/
H A Ddevkit3250_spl.c17 static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
/rk3399_rockchip-uboot/arch/x86/cpu/ivybridge/
H A Dbd82x6x.c24 #define GPIO_BASE 0x48 macro
199 dm_pci_read_config32(dev, GPIO_BASE, &base); in bd82x6x_get_gpio_base()
H A Dlpc.c497 dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1); in bd82x6x_lpc_early_init()
/rk3399_rockchip-uboot/board/renesas/sh7752evb/
H A Dsh7752evb.c24 struct gpio_regs *gpio = GPIO_BASE; in init_gpio()
84 struct gpio_regs *gpio = GPIO_BASE; in init_gether_mdio()
164 struct gpio_regs *gpio = GPIO_BASE; in board_mmc_init()
/rk3399_rockchip-uboot/board/renesas/sh7753evb/
H A Dsh7753evb.c24 struct gpio_regs *gpio = GPIO_BASE; in init_gpio()
91 struct gpio_regs *gpio = GPIO_BASE; in init_gether_mdio()
180 struct gpio_regs *gpio = GPIO_BASE; in board_mmc_init()
/rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/
H A Dcpu.h94 SAMSUNG_BASE(gpio, GPIO_BASE)
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-ivybridge/
H A Dpch.h73 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ macro
96 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ macro
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-broadwell/
H A Dpch.h17 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ macro
/rk3399_rockchip-uboot/arch/sh/include/asm/
H A Dcpu_sh7752.h194 #define GPIO_BASE ((struct gpio_regs *)0xffec0000) macro
H A Dcpu_sh7753.h194 #define GPIO_BASE ((struct gpio_regs *)0xffec0000) macro
/rk3399_rockchip-uboot/arch/x86/cpu/broadwell/
H A Dpch.c46 dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1); in broadwell_pch_early_init()
518 dm_pci_read_config32(dev, GPIO_BASE, gbasep); in broadwell_get_gpio_base()
/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A DKconfig105 config GPIO_BASE config
/rk3399_rockchip-uboot/arch/arm/mach-rmobile/include/mach/
H A Dr8a7740.h19 #define GPIO_BASE 0xE6050000 macro
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h466 #define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) macro