1*e9b3ce3fSVladimir Zapolskiy /*
2*e9b3ce3fSVladimir Zapolskiy * Timll DevKit3250 board support, SPL board configuration
3*e9b3ce3fSVladimir Zapolskiy *
4*e9b3ce3fSVladimir Zapolskiy * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
5*e9b3ce3fSVladimir Zapolskiy *
6*e9b3ce3fSVladimir Zapolskiy * SPDX-License-Identifier: GPL-2.0+
7*e9b3ce3fSVladimir Zapolskiy */
8*e9b3ce3fSVladimir Zapolskiy
9*e9b3ce3fSVladimir Zapolskiy #include <common.h>
10*e9b3ce3fSVladimir Zapolskiy #include <asm/io.h>
11*e9b3ce3fSVladimir Zapolskiy #include <asm/arch/sys_proto.h>
12*e9b3ce3fSVladimir Zapolskiy #include <asm/arch/cpu.h>
13*e9b3ce3fSVladimir Zapolskiy #include <asm/arch/emc.h>
14*e9b3ce3fSVladimir Zapolskiy #include <asm/arch-lpc32xx/gpio.h>
15*e9b3ce3fSVladimir Zapolskiy #include <spl.h>
16*e9b3ce3fSVladimir Zapolskiy
17*e9b3ce3fSVladimir Zapolskiy static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
18*e9b3ce3fSVladimir Zapolskiy
19*e9b3ce3fSVladimir Zapolskiy /*
20*e9b3ce3fSVladimir Zapolskiy * SDRAM K4S561632N-LC60 settings are selected in assumption that
21*e9b3ce3fSVladimir Zapolskiy * SDRAM clock may be set up to 166 MHz, however at the moment
22*e9b3ce3fSVladimir Zapolskiy * it is 104 MHz. Most delay values are converted to be a multiple of
23*e9b3ce3fSVladimir Zapolskiy * base clock, and precise pinned values are not needed here.
24*e9b3ce3fSVladimir Zapolskiy */
25*e9b3ce3fSVladimir Zapolskiy struct emc_dram_settings dram_64mb = {
26*e9b3ce3fSVladimir Zapolskiy .cmddelay = 0x0001C000,
27*e9b3ce3fSVladimir Zapolskiy .config0 = 0x00005682,
28*e9b3ce3fSVladimir Zapolskiy .rascas0 = 0x00000302,
29*e9b3ce3fSVladimir Zapolskiy .rdconfig = 0x00000011, /* undocumented but crucial value */
30*e9b3ce3fSVladimir Zapolskiy
31*e9b3ce3fSVladimir Zapolskiy .trp = 83333333,
32*e9b3ce3fSVladimir Zapolskiy .tras = 23809524,
33*e9b3ce3fSVladimir Zapolskiy .tsrex = 12500000,
34*e9b3ce3fSVladimir Zapolskiy .twr = 83000000, /* tWR = tRDL = 2 CLK */
35*e9b3ce3fSVladimir Zapolskiy .trc = 15384616,
36*e9b3ce3fSVladimir Zapolskiy .trfc = 15384616,
37*e9b3ce3fSVladimir Zapolskiy .txsr = 12500000,
38*e9b3ce3fSVladimir Zapolskiy .trrd = 1,
39*e9b3ce3fSVladimir Zapolskiy .tmrd = 1,
40*e9b3ce3fSVladimir Zapolskiy .tcdlr = 0,
41*e9b3ce3fSVladimir Zapolskiy
42*e9b3ce3fSVladimir Zapolskiy .refresh = 130000, /* 800 clock cycles */
43*e9b3ce3fSVladimir Zapolskiy
44*e9b3ce3fSVladimir Zapolskiy .mode = 0x00018000,
45*e9b3ce3fSVladimir Zapolskiy .emode = 0x02000000,
46*e9b3ce3fSVladimir Zapolskiy };
47*e9b3ce3fSVladimir Zapolskiy
spl_board_init(void)48*e9b3ce3fSVladimir Zapolskiy void spl_board_init(void)
49*e9b3ce3fSVladimir Zapolskiy {
50*e9b3ce3fSVladimir Zapolskiy /* First of all silence buzzer controlled by GPO_20 */
51*e9b3ce3fSVladimir Zapolskiy writel((1 << 20), &gpio->p3_outp_clr);
52*e9b3ce3fSVladimir Zapolskiy
53*e9b3ce3fSVladimir Zapolskiy lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
54*e9b3ce3fSVladimir Zapolskiy preloader_console_init();
55*e9b3ce3fSVladimir Zapolskiy
56*e9b3ce3fSVladimir Zapolskiy ddr_init(&dram_64mb);
57*e9b3ce3fSVladimir Zapolskiy
58*e9b3ce3fSVladimir Zapolskiy /*
59*e9b3ce3fSVladimir Zapolskiy * NAND initialization is done by nand_init(),
60*e9b3ce3fSVladimir Zapolskiy * here just enable NAND SLC clocks
61*e9b3ce3fSVladimir Zapolskiy */
62*e9b3ce3fSVladimir Zapolskiy lpc32xx_slc_nand_init();
63*e9b3ce3fSVladimir Zapolskiy }
64*e9b3ce3fSVladimir Zapolskiy
spl_boot_device(void)65*e9b3ce3fSVladimir Zapolskiy u32 spl_boot_device(void)
66*e9b3ce3fSVladimir Zapolskiy {
67*e9b3ce3fSVladimir Zapolskiy return BOOT_DEVICE_NAND;
68*e9b3ce3fSVladimir Zapolskiy }
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