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/rk3399_rockchip-uboot/drivers/power/power_delivery/
H A Dfusb302_reg.h13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
20 #define FUSB_REG_SWITCHES0_CC1_PD_EN BIT(0)
22 #define FUSB_REG_SWITCHES1_POWERROLE BIT(7)
23 #define FUSB_REG_SWITCHES1_SPECREV1 BIT(6)
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/rk3399_rockchip-uboot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h18 #ifndef BIT
19 #define BIT(nr) (1 << (nr)) macro
343 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
369 #define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30)
370 #define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31)
382 #define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30)
383 #define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31)
385 #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
386 #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
387 #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
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/rk3399_rockchip-uboot/drivers/video/drm/display-serdes/maxim/
H A Dmaxim-max96789.h22 #define CFG_BLOCK BIT(0)
25 #define IIC_2_EN BIT(7)
26 #define IIC_1_EN BIT(6)
27 #define DIS_REM_CC BIT(4)
31 #define VID_TX_EN_U BIT(7)
32 #define VID_TX_EN_Z BIT(6)
33 #define VID_TX_EN_Y BIT(5)
34 #define VID_TX_EN_X BIT(4)
35 #define AUD_TX_EN_Y BIT(3)
36 #define AUD_TX_EN_X BIT(2)
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H A Dmaxim-max96755.h22 #define CFG_BLOCK BIT(0)
25 #define IIC_2_EN BIT(7)
26 #define IIC_1_EN BIT(6)
27 #define DIS_REM_CC BIT(4)
31 #define VID_TX_EN_U BIT(7)
32 #define VID_TX_EN_Z BIT(6)
33 #define VID_TX_EN_Y BIT(5)
34 #define VID_TX_EN_X BIT(4)
35 #define AUD_TX_EN_Y BIT(3)
36 #define AUD_TX_EN_X BIT(2)
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H A Dmaxim-max96745.h22 #define PU_LF3 BIT(3)
23 #define PU_LF2 BIT(2)
24 #define PU_LF1 BIT(1)
25 #define PU_LF0 BIT(0)
28 #define RESET_ALL BIT(7)
29 #define SLEEP BIT(3)
32 #define CXTP_B BIT(2)
33 #define CXTP_A BIT(0)
36 #define LOCKED BIT(3)
37 #define ERROR BIT(2)
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/rk3399_rockchip-uboot/drivers/video/drm/display-serdes/rohm/
H A Drohm-bu18rl82.h258 {BU18RL82_IO_SW_GPIO0, BIT(2) | BIT(1)},
259 {BU18RL82_IO_SW_GPIO1, BIT(2) | BIT(1)},
260 {BU18RL82_IO_SW_GPIO2, BIT(2) | BIT(1)},
261 {BU18RL82_IO_SW_GPIO3, BIT(2) | BIT(1)},
262 {BU18RL82_IO_SW_GPIO4, BIT(2) | BIT(1)},
263 {BU18RL82_IO_SW_GPIO5, BIT(2) | BIT(1)},
264 {BU18RL82_IO_SW_GPIO6, BIT(2) | BIT(1)},
265 {BU18RL82_IO_SW_GPIO7, BIT(2) | BIT(1)},
269 {BU18RL82_IO_OEN_GPIO0, BIT(3)},
270 {BU18RL82_IO_OEN_GPIO1, BIT(3)},
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H A Drohm-bu18tl82.h308 {BU18TL82_IO_SW_GPIO0, BIT(2) | BIT(1)},
309 {BU18TL82_IO_SW_GPIO1, BIT(2) | BIT(1)},
310 {BU18TL82_IO_SW_GPIO2, BIT(2) | BIT(1)},
311 {BU18TL82_IO_SW_GPIO3, BIT(2) | BIT(1)},
312 {BU18TL82_IO_SW_GPIO4, BIT(2) | BIT(1)},
313 {BU18TL82_IO_SW_GPIO5, BIT(2) | BIT(1)},
314 {BU18TL82_IO_SW_GPIO6, BIT(2) | BIT(1)},
315 {BU18TL82_IO_SW_GPIO7, BIT(2) | BIT(1)},
319 {BU18TL82_IO_OEN_GPIO0, BIT(3)},
320 {BU18TL82_IO_OEN_GPIO1, BIT(3)},
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/rk3399_rockchip-uboot/include/
H A Dmax96755f.h19 #define CFG_BLOCK BIT(0)
22 #define IIC_2_EN BIT(7)
23 #define IIC_1_EN BIT(6)
24 #define DIS_REM_CC BIT(4)
28 #define VID_TX_EN_U BIT(7)
29 #define VID_TX_EN_Z BIT(6)
30 #define VID_TX_EN_Y BIT(5)
31 #define VID_TX_EN_X BIT(4)
32 #define AUD_TX_EN_Y BIT(3)
33 #define AUD_TX_EN_X BIT(2)
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H A Dmax96745.h17 #define RESET_ALL BIT(7)
18 #define SLEEP BIT(3)
21 #define CXTP_B BIT(2)
22 #define CXTP_A BIT(0)
25 #define LINK_EN BIT(7)
29 #define RESET_LINK BIT(0)
30 #define RESET_ONESHOT BIT(1)
33 #define LINK_LOCKED BIT(0)
36 #define DIS_REM_CC BIT(7)
40 #define VID_TX_EN BIT(0)
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/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_gvi.h41 #define SYS_CTRL0_GVI_EN BIT(0)
42 #define SYS_CTRL0_AUTO_GATING BIT(1)
43 #define SYS_CTRL0_FRM_RST_EN BIT(2)
44 #define SYS_CTRL0_FRM_RST_MODE BIT(3)
51 #define SYS_CTRL0_CDR_ENDIAN_SWAP BIT(12)
52 #define SYS_CTRL0_PACK_BYTE_SWAP BIT(13)
53 #define SYS_CTRL0_PACK_ENDIAN_SWAP BIT(14)
54 #define SYS_CTRL0_ENC8B10B_ENDIAN_SWAP BIT(15)
55 #define SYS_CTRL0_CDR_EN BIT(16)
56 #define SYS_CTRL0_ALN_EN BIT(17)
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H A Drk628_dsi.h18 #define POWER_UP BIT(0)
25 #define LOOSELY18_EN BIT(8)
28 #define COLORM_ACTIVE_LOW BIT(4)
29 #define SHUTD_ACTIVE_LOW BIT(3)
30 #define HSYNC_ACTIVE_LOW BIT(2)
31 #define VSYNC_ACTIVE_LOW BIT(1)
32 #define DATAEN_ACTIVE_LOW BIT(0)
37 #define CRC_RX_EN BIT(4)
38 #define ECC_RX_EN BIT(3)
39 #define BTA_EN BIT(2)
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/rk3399_rockchip-uboot/arch/arm/mach-socfpga/include/mach/
H A Dreset_manager_arria10.h84 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
85 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
86 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
87 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
88 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
89 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
90 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
91 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
92 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
93 #define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
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H A Dfpga_manager_arria10.h11 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
12 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
13 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
14 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
15 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
16 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
17 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
18 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
19 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
20 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
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/rk3399_rockchip-uboot/include/dt-bindings/suspend/
H A Drockchip-rk3528.h13 #ifndef BIT
14 #define BIT(nr) (1 << (nr)) macro
17 #define RKPM_SLP_ARMPD BIT(0)
18 #define RKPM_SLP_ARMOFF BIT(1)
19 #define RKPM_SLP_ARMOFF_DDRPD BIT(2)
20 #define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
23 #define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
24 #define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
25 #define RKPM_SLP_PMU_DIS_OSC BIT(10)
27 #define RKPM_SLP_CLK_GT BIT(16)
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H A Drockchip-rv1126.h13 #ifndef BIT
14 #define BIT(nr) (1 << (nr)) macro
17 #define RKPM_SLP_ARMPD BIT(0)
18 #define RKPM_SLP_ARMOFF BIT(1)
19 #define RKPM_SLP_ARMOFF_DDRPD BIT(2)
20 #define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
23 #define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
24 #define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
25 #define RKPM_SLP_PMU_DIS_OSC BIT(10)
27 #define RKPM_SLP_CLK_GT BIT(16)
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dlvds_rk3288.h11 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
12 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
13 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
14 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
15 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
16 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
17 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
18 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
21 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
22 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)
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/rk3399_rockchip-uboot/drivers/usb/cdns3/
H A Dgadget.h124 #define USB_CONF_CFGRST BIT(0)
126 #define USB_CONF_CFGSET BIT(1)
128 #define USB_CONF_USB3DIS BIT(3)
130 #define USB_CONF_USB2DIS BIT(4)
132 #define USB_CONF_LENDIAN BIT(5)
138 #define USB_CONF_BENDIAN BIT(6)
140 #define USB_CONF_SWRST BIT(7)
142 #define USB_CONF_DSING BIT(8)
144 #define USB_CONF_DMULT BIT(9)
146 #define USB_CONF_DMAOFFEN BIT(10)
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/rk3399_rockchip-uboot/drivers/video/drm/
H A Dinno_hdmi.h32 #define m_RST_ANALOG BIT(6)
34 #define v_NOT_RST_ANALOG BIT(6)
35 #define m_RST_DIGITAL BIT(5)
37 #define v_NOT_RST_DIGITAL BIT(5)
38 #define m_REG_CLK_INV BIT(4)
40 #define v_REG_CLK_INV BIT(4)
41 #define m_VCLK_INV BIT(3)
43 #define v_VCLK_INV BIT(3)
44 #define m_REG_CLK_SOURCE BIT(2)
46 #define v_REG_CLK_SOURCE_SYS BIT(2)
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/rk3399_rockchip-uboot/drivers/net/
H A Dpic32_eth.h59 #define ETHCON_BUFCDEC BIT(0)
60 #define ETHCON_RXEN BIT(8)
61 #define ETHCON_TXRTS BIT(9)
62 #define ETHCON_ON BIT(15)
69 #define ETHSTAT_BUSY BIT(7)
73 #define ETHRXFC_BCEN BIT(0)
74 #define ETHRXFC_MCEN BIT(1)
75 #define ETHRXFC_UCEN BIT(3)
76 #define ETHRXFC_RUNTEN BIT(4)
77 #define ETHRXFC_CRCOKEN BIT(5)
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/rk3399_rockchip-uboot/include/dt-bindings/media/
H A Drockchip_mipi_dsi.h10 #define BIT(nr) (1UL << (nr)) macro
13 #define MIPI_DSI_MSG_REQ_ACK BIT(0)
15 #define MIPI_DSI_MSG_USE_LPM BIT(1)
20 #define MIPI_DSI_MODE_VIDEO BIT(0)
22 #define MIPI_DSI_MODE_VIDEO_BURST BIT(1)
24 #define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2)
26 #define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3)
28 #define MIPI_DSI_MODE_VIDEO_HSE BIT(4)
30 #define MIPI_DSI_MODE_VIDEO_HFP BIT(5)
32 #define MIPI_DSI_MODE_VIDEO_HBP BIT(6)
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/rk3399_rockchip-uboot/arch/arm/mach-uniphier/dram/
H A Dddrmphy-regs.h18 #define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */
19 #define MPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
20 #define MPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
21 #define MPHY_PIR_DCAL BIT(5) /* DDL Calibration */
22 #define MPHY_PIR_PHYRST BIT(6) /* PHY Reset */
23 #define MPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
24 #define MPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
25 #define MPHY_PIR_WL BIT(9) /* Write Leveling */
26 #define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
27 #define MPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
[all …]
H A Dddrphy-regs.h17 #define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
18 #define PHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
19 #define PHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
20 #define PHY_PIR_DCAL BIT(5) /* DDL Calibration */
21 #define PHY_PIR_PHYRST BIT(6) /* PHY Reset */
22 #define PHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
23 #define PHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
24 #define PHY_PIR_WL BIT(9) /* Write Leveling */
25 #define PHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
26 #define PHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
[all …]
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Ddenali.h17 #define DEVICE_RESET__BANK(bank) BIT(bank)
20 #define TRANSFER_SPARE_REG__FLAG BIT(0)
35 #define RB_PIN_ENABLED__BANK(bank) BIT(bank)
38 #define MULTIPLANE_OPERATION__FLAG BIT(0)
41 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
44 #define COPYBACK_DISABLE__FLAG BIT(0)
47 #define CACHE_WRITE_ENABLE__FLAG BIT(0)
50 #define CACHE_READ_ENABLE__FLAG BIT(0)
53 #define PREFETCH_MODE__PREFETCH_EN BIT(0)
57 #define CHIP_EN_DONT_CARE__FLAG BIT(0)
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/rk3399_rockchip-uboot/drivers/phy/marvell/
H A Dcomphy_a3700.h28 #define rb_pin_pu_iveref BIT(1)
29 #define rb_pin_reset_core BIT(11)
30 #define rb_pin_reset_comphy BIT(12)
31 #define rb_pin_pu_pll BIT(16)
32 #define rb_pin_pu_rx BIT(17)
33 #define rb_pin_pu_tx BIT(18)
34 #define rb_pin_tx_idle BIT(19)
39 #define rb_phy_rx_init BIT(30)
42 #define rb_rx_init_done BIT(0)
43 #define rb_pll_ready_rx BIT(2)
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/rk3399_rockchip-uboot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3308.c22 .route_val = BIT(16 + 0) | BIT(0),
29 .route_val = BIT(16 + 2) | BIT(16 + 3),
36 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
43 .route_val = BIT(16 + 4),
50 .route_val = BIT(16 + 4) | BIT(4),
57 .route_val = BIT(16 + 3),
64 .route_val = BIT(16 + 3),
71 .route_val = BIT(16 + 3) | BIT(3),
78 .route_val = BIT(16 + 3) | BIT(3),
85 .route_val = BIT(16 + 12) | BIT(16 + 13),
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