phy/marvell/comphy_a3700.h

28 #define rb_pin_pu_iveref		BIT(1)
29 #define rb_pin_reset_core		BIT(11)
30 #define rb_pin_reset_comphy		BIT(12)
31 #define rb_pin_pu_pll			BIT(16)
32 #define rb_pin_pu_rx			BIT(17)
33 #define rb_pin_pu_tx			BIT(18)
34 #define rb_pin_tx_idle			BIT(19)
39 #define rb_phy_rx_init			BIT(30)
42 #define rb_rx_init_done			BIT(0)
43 #define rb_pll_ready_rx			BIT(2)
44 #define rb_pll_ready_tx			BIT(3)
78 #define usb32_ctrl_id_mode		BIT(0)
79 #define usb32_ctrl_soft_id		BIT(1)
80 #define usb32_ctrl_int_mode		BIT(4)
96 #define rb_use_max_pll_rate		BIT(12)
97 #define rb_force_calibration_done	BIT(9)
110 #define phy_txd_inv			BIT(10)
111 #define phy_rxd_inv			BIT(11)
117 #define rb_idle_sync_en			BIT(12)
123 #define g2_tx_ssc_amp			BIT(14)
134 #define rb_clk100m_125m_en		BIT(4)
135 #define rb_clk500m_en			BIT(7)
136 #define rb_ref_clk_sel			BIT(10)
142 #define rb_ref1m_gen_div_force		BIT(8)
150 #define rb_fast_dfe_enable		BIT(13)
153 #define bf_sel_bits_pcie_force		BIT(15)
156 #define bf_use_max_pll_rate		BIT(9)
158 #define bf_use_max_pll_rate		BIT(9)
161 #define bf_spread_spectrum_clock_en	BIT(7)
164 #define rb_txdclk_pclk_en		BIT(0)
167 #define bf_soft_rst			BIT(0)
169 #define rb_mode_core_clk_freq_sel	BIT(9)
170 #define rb_mode_pipe_width_32		BIT(3)
173 #define rb_mode_margin_override		BIT(2)
176 #define bf_cfg_sel_20b			BIT(15)
187 #define rb_usb2phy_suspm		BIT(14)
188 #define rb_usb2phy_pu			BIT(0)
191 #define rb_pu_otg			BIT(4)
194 #define rb_cdp_en			BIT(2)
195 #define rb_dcp_en			BIT(3)
196 #define rb_pd_en			BIT(4)
197 #define rb_pu_chrg_dtc			BIT(5)
198 #define rb_cdp_dm_auto			BIT(7)
199 #define rb_enswitch_dp			BIT(12)
200 #define rb_enswitch_dm			BIT(13)
203 #define rb_usb2phy_pllcal_done		BIT(31)
204 #define rb_usb2phy_impcal_done		BIT(23)
207 #define rb_usb2phy_pll_ready		BIT(31)
210 #define rb_usb2phy_sqcal_done		BIT(31)
213 #define rb_usb2phy2_suspm		BIT(7)
214 #define rb_usb2phy2_pu			BIT(0)
244 #define bs_txd_inv			BIT(10)
245 #define bs_rxd_inv			BIT(11)
254 #define bs_max_pll_rate			BIT(12)
257 #define bs_phyctrl_frm_pin		BIT(13)
260 #define bs_phy_pu_pll			BIT(6)