Lines Matching refs:BIT
17 #define DEVICE_RESET__BANK(bank) BIT(bank)
20 #define TRANSFER_SPARE_REG__FLAG BIT(0)
35 #define RB_PIN_ENABLED__BANK(bank) BIT(bank)
38 #define MULTIPLANE_OPERATION__FLAG BIT(0)
41 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
44 #define COPYBACK_DISABLE__FLAG BIT(0)
47 #define CACHE_WRITE_ENABLE__FLAG BIT(0)
50 #define CACHE_READ_ENABLE__FLAG BIT(0)
53 #define PREFETCH_MODE__PREFETCH_EN BIT(0)
57 #define CHIP_EN_DONT_CARE__FLAG BIT(0)
60 #define ECC_ENABLE__FLAG BIT(0)
63 #define GLOBAL_INT_EN_FLAG BIT(0)
96 #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
99 #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
143 #define WRITE_PROTECT__FLAG BIT(0)
186 #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
197 #define FEATURES__DMA BIT(6)
198 #define FEATURES__CMD_DMA BIT(7)
199 #define FEATURES__PARTITION BIT(8)
200 #define FEATURES__XDMA_SIDEBAND BIT(9)
201 #define FEATURES__GPREG BIT(10)
202 #define FEATURES__INDEX_ADDR BIT(11)
210 #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
211 #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
212 #define INTR__ECC_ERR BIT(1) /* old IP */
213 #define INTR__DMA_CMD_COMP BIT(2)
214 #define INTR__TIME_OUT BIT(3)
215 #define INTR__PROGRAM_FAIL BIT(4)
216 #define INTR__ERASE_FAIL BIT(5)
217 #define INTR__LOAD_COMP BIT(6)
218 #define INTR__PROGRAM_COMP BIT(7)
219 #define INTR__ERASE_COMP BIT(8)
220 #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
221 #define INTR__LOCKED_BLK BIT(10)
222 #define INTR__UNSUP_CMD BIT(11)
223 #define INTR__INT_ACT BIT(12)
224 #define INTR__RST_COMP BIT(13)
225 #define INTR__PIPE_CMD_ERR BIT(14)
226 #define INTR__PAGE_XFER_INC BIT(15)
227 #define INTR__ERASED_PAGE BIT(16)
250 #define ERR_CORRECTION_INFO__UNCOR BIT(14)
251 #define ERR_CORRECTION_INFO__LAST_ERR BIT(15)
256 #define ECC_COR_INFO__UNCOR_ERR BIT(7)
267 #define DMA_ENABLE__FLAG BIT(0)
270 #define IGNORE_ECC_DONE__FLAG BIT(0)
274 #define DMA_INTR__TARGET_ERROR BIT(0)
275 #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
276 #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
277 #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
278 #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
279 #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
288 #define CHNL_ACTIVE__CHANNEL0 BIT(0)
289 #define CHNL_ACTIVE__CHANNEL1 BIT(1)
290 #define CHNL_ACTIVE__CHANNEL2 BIT(2)
291 #define CHNL_ACTIVE__CHANNEL3 BIT(3)
323 #define DENALI_CAP_HW_ECC_FIXUP BIT(0)
324 #define DENALI_CAP_DMA_64BIT BIT(1)