1*b36e944aSJoseph Chen /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*b36e944aSJoseph Chen /* 3*b36e944aSJoseph Chen * Header providing constants for Rockchip suspend bindings. 4*b36e944aSJoseph Chen * 5*b36e944aSJoseph Chen * Copyright (C) 2022, Rockchip Electronics Co., Ltd 6*b36e944aSJoseph Chen * Author: XiaoDong.Huang 7*b36e944aSJoseph Chen */ 8*b36e944aSJoseph Chen 9*b36e944aSJoseph Chen #ifndef __DT_BINDINGS_RK3528_PM_H__ 10*b36e944aSJoseph Chen #define __DT_BINDINGS_RK3528_PM_H__ 11*b36e944aSJoseph Chen /******************************bits ops************************************/ 12*b36e944aSJoseph Chen 13*b36e944aSJoseph Chen #ifndef BIT 14*b36e944aSJoseph Chen #define BIT(nr) (1 << (nr)) 15*b36e944aSJoseph Chen #endif 16*b36e944aSJoseph Chen 17*b36e944aSJoseph Chen #define RKPM_SLP_ARMPD BIT(0) 18*b36e944aSJoseph Chen #define RKPM_SLP_ARMOFF BIT(1) 19*b36e944aSJoseph Chen #define RKPM_SLP_ARMOFF_DDRPD BIT(2) 20*b36e944aSJoseph Chen #define RKPM_SLP_ARMOFF_LOGOFF BIT(3) 21*b36e944aSJoseph Chen 22*b36e944aSJoseph Chen /* all plls except ddr's pll*/ 23*b36e944aSJoseph Chen #define RKPM_SLP_PMU_HW_PLLS_PD BIT(8) 24*b36e944aSJoseph Chen #define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) 25*b36e944aSJoseph Chen #define RKPM_SLP_PMU_DIS_OSC BIT(10) 26*b36e944aSJoseph Chen 27*b36e944aSJoseph Chen #define RKPM_SLP_CLK_GT BIT(16) 28*b36e944aSJoseph Chen #define RKPM_SLP_PMIC_LP BIT(17) 29*b36e944aSJoseph Chen 30*b36e944aSJoseph Chen #define RKPM_SLP_32K_EXT BIT(24) 31*b36e944aSJoseph Chen #define RKPM_SLP_TIME_OUT_WKUP BIT(25) 32*b36e944aSJoseph Chen #define RKPM_SLP_PMU_DBG BIT(26) 33*b36e944aSJoseph Chen 34*b36e944aSJoseph Chen /* the wake up source */ 35*b36e944aSJoseph Chen #define RKPM_CPU0_WKUP_EN BIT(0) 36*b36e944aSJoseph Chen #define RKPM_CPU1_WKUP_EN BIT(1) 37*b36e944aSJoseph Chen #define RKPM_CPU2_WKUP_EN BIT(2) 38*b36e944aSJoseph Chen #define RKPM_CPU3_WKUP_EN BIT(3) 39*b36e944aSJoseph Chen #define RKPM_GPIO_WKUP_EN BIT(4) 40*b36e944aSJoseph Chen #define RKPM_HDMI_HDP_WKUP_EN BIT(5) 41*b36e944aSJoseph Chen #define RKPM_HDMI_CEC_WKUP_EN BIT(6) 42*b36e944aSJoseph Chen #define RKPM_PWMIR_WKUP_EN BIT(7) 43*b36e944aSJoseph Chen #define RKPM_GMAC_WKUP_EN BIT(8) 44*b36e944aSJoseph Chen #define RKPM_TIMER_WKUP_EN BIT(9) 45*b36e944aSJoseph Chen #define RKPM_USBDEV_WKUP_EN BIT(10) 46*b36e944aSJoseph Chen #define RKPM_SYSINT_WKUP_EN BIT(11) 47*b36e944aSJoseph Chen #define RKPM_TIME_OUT_WKUP_EN BIT(12) 48*b36e944aSJoseph Chen 49*b36e944aSJoseph Chen /* the pwm regulator */ 50*b36e944aSJoseph Chen #define RKPM_PWM0_M0_REGULATOR_EN BIT(0) 51*b36e944aSJoseph Chen #define RKPM_PWM1_M0_REGULATOR_EN BIT(1) 52*b36e944aSJoseph Chen #define RKPM_PWM2_M0_REGULATOR_EN BIT(2) 53*b36e944aSJoseph Chen 54*b36e944aSJoseph Chen #endif 55