Lines Matching refs:BIT
18 #define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */
19 #define MPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
20 #define MPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
21 #define MPHY_PIR_DCAL BIT(5) /* DDL Calibration */
22 #define MPHY_PIR_PHYRST BIT(6) /* PHY Reset */
23 #define MPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
24 #define MPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
25 #define MPHY_PIR_WL BIT(9) /* Write Leveling */
26 #define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
27 #define MPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
28 #define MPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
29 #define MPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
30 #define MPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
31 #define MPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
32 #define MPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
33 #define MPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
35 #define MPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
37 #define MPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
39 #define MPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
40 #define MPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
43 #define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
44 #define MPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
45 #define MPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
46 #define MPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
47 #define MPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
48 #define MPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
49 #define MPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
50 #define MPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
51 #define MPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
52 #define MPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
53 #define MPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
54 #define MPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
55 #define MPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
56 #define MPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
57 #define MPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
58 #define MPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
59 #define MPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
60 #define MPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
61 #define MPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
62 #define MPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
64 #define MPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
113 #define MPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
114 #define MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */