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Searched refs:read_mpidr (Results 1 – 25 of 64) sorted by relevance

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/rk3399_ARM-atf/bl32/tsp/
H A Dtsp_interrupt.c39 read_mpidr(), elr_el3); in tsp_update_sync_sel1_intr_stats()
42 read_mpidr(), in tsp_update_sync_sel1_intr_stats()
58 read_mpidr(), tsp_stats[linear_id].preempt_intr_count); in tsp_handle_preemption()
111 read_mpidr(), id); in tsp_common_int_handler()
113 read_mpidr(), tsp_stats[linear_id].sel1_intr_count); in tsp_common_int_handler()
H A Dtsp_main.c51 read_mpidr(), in tsp_main()
77 INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); in tsp_cpu_on_main()
79 read_mpidr(), in tsp_cpu_on_main()
114 INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); in tsp_cpu_off_main()
116 read_mpidr(), in tsp_cpu_off_main()
154 read_mpidr(), in tsp_cpu_suspend_main()
188 read_mpidr(), max_off_pwrlvl); in tsp_cpu_resume_main()
190 read_mpidr(), in tsp_cpu_resume_main()
224 INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(), in tsp_smc_handler()
227 INFO("TSP: cpu 0x%lx: %u smcs, %u erets\n", read_mpidr(), in tsp_smc_handler()
H A Dtsp_common.c99 INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr()); in tsp_system_off_main()
100 INFO("TSP: cpu 0x%lx: %u smcs, %u erets requests\n", read_mpidr(), in tsp_system_off_main()
127 INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr()); in tsp_system_reset_main()
128 INFO("TSP: cpu 0x%lx: %u smcs, %u erets requests\n", read_mpidr(), in tsp_system_reset_main()
H A Dtsp_ffa_main.c303 VERBOSE("TSP: cpu 0x%lx off request\n", read_mpidr()); in tsp_cpu_off_main()
305 read_mpidr(), in tsp_cpu_off_main()
342 read_mpidr(), in tsp_cpu_suspend_main()
375 read_mpidr(), max_off_pwrlvl); in tsp_cpu_resume_main()
377 read_mpidr(), in tsp_cpu_resume_main()
617 read_mpidr(), in tsp_main()
645 VERBOSE("TSP: cpu 0x%lx turned on\n", read_mpidr()); in tsp_cpu_on_main()
647 read_mpidr(), in tsp_cpu_on_main()
/rk3399_ARM-atf/services/spd/tlkd/
H A Dtlkd_pm.c43 int cpu = read_mpidr() & MPIDR_CPU_MASK; in cpu_suspend_handler()
75 int cpu = read_mpidr() & MPIDR_CPU_MASK; in cpu_resume_handler()
/rk3399_ARM-atf/plat/rockchip/common/aarch64/
H A Dplatform_common.c91 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
98 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
/rk3399_ARM-atf/plat/mediatek/mt8173/aarch64/
H A Dplatform_common.c83 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
88 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
/rk3399_ARM-atf/plat/mediatek/mt8183/aarch64/
H A Dplatform_common.c72 cci_enable_cluster_coherency(read_mpidr()); in plat_mtk_cci_enable()
77 cci_disable_cluster_coherency(read_mpidr()); in plat_mtk_cci_disable()
/rk3399_ARM-atf/plat/renesas/common/
H A Dbl31_plat_setup.c61 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
66 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_pm.c39 curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); in hikey_pwr_domain_on()
55 mpidr = read_mpidr(); in hikey_pwr_domain_on_finish()
81 mpidr = read_mpidr(); in hikey_pwr_domain_off()
H A Dhikey_bl1_setup.c162 ep_info->args.arg0 = 0xffff & read_mpidr(); in bl1_plat_set_ep_info()
/rk3399_ARM-atf/plat/rpi/common/
H A Drpi3_topology.c50 if ((read_mpidr() & MPIDR_MT_MASK) != 0) { in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/mediatek/mt8192/
H A Dplat_topology.c45 if (read_mpidr() & MPIDR_MT_MASK) { in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/mediatek/mt8195/
H A Dplat_topology.c40 if ((read_mpidr() & MPIDR_MT_MASK) != 0) { in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/mediatek/mt8186/
H A Dplat_topology.c40 if ((read_mpidr() & MPIDR_MT_MASK) != 0) { in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/services/spd/pncd/
H A Dpncd_main.c150 if (read_mpidr() != pncd_sp_context.mpidr) { in pncd_context_switch_to()
328 assert(ns != 0 || read_mpidr() == pncd_sp_context.mpidr); in pncd_smc_handler_unsafe()
407 plat_ic_raise_ns_sgi(SPD_PNCD_NS_IRQ, read_mpidr()); in pncd_smc_handler_unsafe()
H A Dpncd_common.c36 pnc_ctx->mpidr = read_mpidr(); in pncd_init_pnc_ep_state()
/rk3399_ARM-atf/plat/brcm/board/common/
H A Dtimer_sync.c69 cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); in brcm_timer_sync_init()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/
H A Dplat_psci_handlers.c107 int core_pos = read_mpidr() & MPIDR_CPU_MASK; in tegra_soc_get_target_pwr_state()
196 u_register_t mpidr = read_mpidr(); in tegra_soc_pwr_domain_suspend()
343 u_register_t mpidr = read_mpidr(); in tegra_soc_pwr_domain_power_down_wfi()
590 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); in tegra_soc_pwr_domain_off()
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dpm.c61 unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); in brcm_pwr_domain_on_finish()
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_pm.c328 uint64_t mpidr = read_mpidr(); in plat_mtk_power_domain_off()
347 uint64_t mpidr = read_mpidr(); in plat_mtk_power_domain_on_finish()
363 uint64_t mpidr = read_mpidr(); in plat_mtk_power_domain_suspend()
404 uint64_t mpidr = read_mpidr(); in plat_mtk_power_domain_suspend_finish()
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/flowctrl/
H A Dflowctrl.c86 unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_fc_ccplex_pgexit_lock()
178 unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_fc_is_ccx_allowed()
/rk3399_ARM-atf/plat/allwinner/sun50i_h6/
H A Dsunxi_power.c117 u_register_t mpidr = read_mpidr(); in sunxi_cpu_power_off_self()
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmarvell_bl2_setup.c129 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in marvell_bl2_handle_post_image_load()
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/pmc/
H A Dpmc.c105 int i, cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_pmc_is_last_on_cpu()

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