1 /*
2 * Copyright (c) 2013-2025, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/arm/cci.h>
16 #include <lib/utils.h>
17 #include <lib/xlat_tables/xlat_tables_compat.h>
18
19 #include <plat_private.h>
20
21 #ifdef PLAT_RK_CCI_BASE
22 static const int cci_map[] = {
23 PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX,
24 PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX
25 };
26 #endif
27
28 /******************************************************************************
29 * Macro generating the code for the function setting up the pagetables as per
30 * the platform memory map & initialize the mmu, for the given exception level
31 ******************************************************************************/
32 #define DEFINE_CONFIGURE_MMU_EL(_el) \
33 void plat_configure_mmu_el ## _el(unsigned long total_base, \
34 unsigned long total_size, \
35 unsigned long ro_start, \
36 unsigned long ro_limit, \
37 unsigned long coh_start, \
38 unsigned long coh_limit) \
39 { \
40 mmap_add_region(total_base, total_base, \
41 total_size, \
42 MT_MEMORY | MT_RW | MT_SECURE); \
43 mmap_add_region(ro_start, ro_start, \
44 ro_limit - ro_start, \
45 MT_MEMORY | MT_RO | MT_SECURE); \
46 if ((coh_limit - coh_start) != 0) \
47 mmap_add_region(coh_start, coh_start, \
48 coh_limit - coh_start, \
49 MT_DEVICE | MT_RW | MT_SECURE); \
50 mmap_add(plat_rk_mmap); \
51 rockchip_plat_mmu_el##_el(); \
52 init_xlat_tables(); \
53 \
54 enable_mmu_el ## _el(0); \
55 }
56
57 /* Define EL3 variants of the function initialising the MMU */
58 DEFINE_CONFIGURE_MMU_EL(3)
59
plat_get_syscnt_freq2(void)60 unsigned int plat_get_syscnt_freq2(void)
61 {
62 #ifdef SYS_COUNTER_FREQ_IN_TICKS
63 return SYS_COUNTER_FREQ_IN_TICKS;
64 #else
65 static int sys_counter_freq_in_hz;
66
67 if (sys_counter_freq_in_hz == 0)
68 sys_counter_freq_in_hz = read_cntfrq_el0();
69
70 assert(sys_counter_freq_in_hz != 0);
71
72 return sys_counter_freq_in_hz;
73 #endif
74 }
75
plat_cci_init(void)76 void plat_cci_init(void)
77 {
78 #ifdef PLAT_RK_CCI_BASE
79 /* Initialize CCI driver */
80 cci_init(PLAT_RK_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
81 #endif
82 }
83
plat_cci_enable(void)84 void plat_cci_enable(void)
85 {
86 /*
87 * Enable CCI coherency for this cluster.
88 * No need for locks as no other cpu is active at the moment.
89 */
90 #ifdef PLAT_RK_CCI_BASE
91 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
92 #endif
93 }
94
plat_cci_disable(void)95 void plat_cci_disable(void)
96 {
97 #ifdef PLAT_RK_CCI_BASE
98 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
99 #endif
100 }
101