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Searched refs:rate (Results 1 – 25 of 36) sorted by relevance

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/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c153 unsigned int rate; member
189 .rate = _rate##U, \
287 static int clk_scmi_dsu_set_rate(rk_scmi_clock_t *clock, unsigned long rate);
296 if (freq_hz == table[i].rate) in rkclk_get_pvtpll_config()
302 static int clk_cpul_set_rate(unsigned long rate, enum pll_type_sel type) in clk_cpul_set_rate() argument
307 if (rate == 0) in clk_cpul_set_rate()
311 sys_clk_info.cpul_rate_count, rate); in clk_cpul_set_rate()
346 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpul_set_rate()
362 static int clk_scmi_cpul_set_rate(rk_scmi_clock_t *clock, unsigned long rate) in clk_scmi_cpul_set_rate() argument
366 if (rate == 0) in clk_scmi_cpul_set_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.c129 unsigned int rate; member
142 .rate = _rate##U, \
154 .rate = _rate##U, \
248 freq = pvtpll[i].rate / 1000000; in rk3568_adjust_pvtpll_table()
256 unsigned long rate) in rockchip_get_pvtpll_length() argument
261 if (rate == table[i].rate) in rockchip_get_pvtpll_length()
273 if (freq_hz == rk3568_cpu_pvtpll_table[i].rate) in rkclk_get_pll_config()
279 static int rk3568_apll_set_rate(unsigned long rate, enum pll_type_sel type) in rk3568_apll_set_rate() argument
284 div = rkclk_get_pll_config(rate); in rk3568_apll_set_rate()
380 static int clk_cpu_set_rate(unsigned long rate, enum pll_type_sel type) in clk_cpu_set_rate() argument
[all …]
/rk3399_ARM-atf/fdts/
H A Dstm32mp15-pinctrl.dtsi27 slew-rate = <1>;
42 slew-rate = <0>;
52 slew-rate = <3>;
65 slew-rate = <1>;
78 slew-rate = <1>;
88 slew-rate = <1>;
98 slew-rate = <1>;
110 slew-rate = <1>;
116 slew-rate = <2>;
128 slew-rate = <1>;
[all …]
H A Dstm32mp25-pinctrl.dtsi16 slew-rate = <0>;
28 slew-rate = <2>;
34 slew-rate = <3>;
48 slew-rate = <1>;
54 slew-rate = <2>;
68 slew-rate = <1>;
74 slew-rate = <2>;
87 slew-rate = <1>;
99 slew-rate = <0>;
H A Dstm32mp13-pinctrl.dtsi16 slew-rate = <0>;
28 slew-rate = <1>;
38 slew-rate = <1>;
52 slew-rate = <1>;
62 slew-rate = <1>;
74 slew-rate = <0>;
89 slew-rate = <0>;
104 slew-rate = <0>;
/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_drv.c38 unsigned long rate, unsigned long *orate,
42 unsigned long *rate,
799 unsigned long *rate, unsigned int depth) in get_dfs_freq() argument
817 return get_module_rate(dfs->parent, drv, rate, ldepth); in get_dfs_freq()
1079 unsigned long *rate, unsigned int depth) in get_part_block_link_freq() argument
1090 return get_module_rate(block->parent, drv, rate, ldepth); in get_part_block_link_freq()
1212 unsigned long rate, unsigned long *orate, in set_cgm_div_freq() argument
1228 cgm_div->freq = rate; in set_cgm_div_freq()
1229 *orate = rate; in set_cgm_div_freq()
1258 unsigned long *rate, unsigned int depth) in get_cgm_div_freq() argument
[all …]
/rk3399_ARM-atf/plat/rockchip/common/scmi/
H A Dscmi_clock.c87 unsigned long rate = 0; in plat_scmi_clock_get_rate() local
94 rate = clock->clk_ops->get_rate(clock); in plat_scmi_clock_get_rate()
97 if (rate == 0) in plat_scmi_clock_get_rate()
98 rate = clock->cur_rate; in plat_scmi_clock_get_rate()
100 return rate; in plat_scmi_clock_get_rate()
105 unsigned long rate) in plat_scmi_clock_set_rate() argument
115 status = clock->clk_ops->set_rate(clock, rate); in plat_scmi_clock_set_rate()
117 clock->cur_rate = rate; in plat_scmi_clock_set_rate()
H A Drockchip_common_clock.c72 int clk_scmi_common_set_rate(rk_scmi_clock_t *clock, unsigned long rate) in clk_scmi_common_set_rate() argument
77 if ((rate == 0) || in clk_scmi_common_set_rate()
85 div = DIV_ROUND_UP(parent_rate, rate); in clk_scmi_common_set_rate()
95 if (abs(rate - now) < abs(rate - best_rate)) { in clk_scmi_common_set_rate()
108 div = DIV_ROUND_UP(parent_rate, rate); in clk_scmi_common_set_rate()
112 if (abs(rate - now) < abs(rate - best_rate)) { in clk_scmi_common_set_rate()
H A Dscmi_clock.h18 int (*set_rate)(struct rk_scmi_clock *clock, unsigned long rate);
54 int clk_scmi_common_set_rate(rk_scmi_clock_t *clock, unsigned long rate);
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c198 unsigned int rate; member
258 .rate = _rate##U, \
371 static int clk_scmi_cci_set_rate(rk_scmi_clock_t *clock, unsigned long rate);
380 if (freq_hz == table[i].rate) in rkclk_get_pvtpll_config()
400 static int clk_cpul_set_rate(unsigned long rate, enum pll_type_sel type) in clk_cpul_set_rate() argument
405 if (rate == 0) in clk_cpul_set_rate()
409 sys_clk_info.cpul_rate_count, rate); in clk_cpul_set_rate()
458 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpul_set_rate()
471 static int clk_scmi_cpul_set_rate(rk_scmi_clock_t *clock, unsigned long rate) in clk_scmi_cpul_set_rate() argument
475 if (rate == 0) in clk_scmi_cpul_set_rate()
[all …]
/rk3399_ARM-atf/plat/aspeed/ast2700/
H A Dplat_bl31_setup.c144 uint32_t rate = 0; in plat_get_pll_rate() local
164 rate = 1900000000; in plat_get_pll_rate()
167 rate = 1800000000; in plat_get_pll_rate()
170 rate = 1700000000; in plat_get_pll_rate()
173 rate = 2000000000; in plat_get_pll_rate()
189 rate = ((CLKIN_25M * mul) / div); in plat_get_pll_rate()
192 return rate; in plat_get_pll_rate()
/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp_clkfunc.c354 void stm32mp_stgen_config(unsigned long rate) in stm32mp_stgen_config() argument
361 if (cntfid0 == rate) { in stm32mp_stgen_config()
368 counter = stm32mp_stgen_get_counter() * rate / cntfid0; in stm32mp_stgen_config()
371 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); in stm32mp_stgen_config()
374 write_cntfrq_el0(rate); in stm32mp_stgen_config()
385 unsigned long rate; in stm32mp_stgen_restore_rate() local
387 rate = mmio_read_32(STGEN_BASE + CNTFID_OFF); in stm32mp_stgen_restore_rate()
389 write_cntfrq_el0((u_register_t)rate); in stm32mp_stgen_restore_rate()
H A Dclk-stm32-core.h46 unsigned long (*recalc_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate);
48 int (*set_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate,
191 unsigned long rate, unsigned long parent_rate);
193 int clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
308 unsigned long rate; member
316 .rate = (_rate),\
/rk3399_ARM-atf/include/drivers/
H A Dclk.h16 int (*set_rate)(unsigned long id, unsigned long rate,
27 int clk_set_rate(unsigned long id, unsigned long rate, unsigned long *orate);
/rk3399_ARM-atf/drivers/clk/
H A Dclk.c37 int clk_set_rate(unsigned long id, unsigned long rate, unsigned long *orate) in clk_set_rate() argument
44 return ops->set_rate(id, rate, orate); in clk_set_rate()
48 return ops->set_rate(id, rate, &lrate); in clk_set_rate()
/rk3399_ARM-atf/drivers/scmi-msg/
H A Dclock.c96 unsigned long rate __unused) in plat_scmi_clock_set_rate()
384 unsigned long rate = 0U; in scmi_clock_rate_get() local
402 rate = plat_scmi_clock_get_rate(msg->agent_id, clock_id); in scmi_clock_rate_get()
404 return_values.rate[0] = (uint32_t)rate; in scmi_clock_rate_get()
405 return_values.rate[1] = (uint32_t)((uint64_t)rate >> 32); in scmi_clock_rate_get()
413 unsigned long rate = 0U; in scmi_clock_rate_set() local
429 rate = (unsigned long)(((uint64_t)in_args->rate[1] << 32) | in scmi_clock_rate_set()
430 in_args->rate[0]); in scmi_clock_rate_set()
432 status = plat_scmi_clock_set_rate(msg->agent_id, clock_id, rate); in scmi_clock_rate_set()
H A Dclock.h62 uint32_t rate[2]; member
90 uint32_t rate[2]; member
/rk3399_ARM-atf/plat/imx/imx8qx/
H A Dimx8qx_bl31_setup.c116 unsigned int diff1, diff2, tmp, rate; in lpuart32_serial_setbrg() local
121 sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); in lpuart32_serial_setbrg()
127 tmp_sbr = (rate / (baudrate * tmp_osr)); in lpuart32_serial_setbrg()
132 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate; in lpuart32_serial_setbrg()
133 diff2 = rate / (tmp_osr * (tmp_sbr + 1)); in lpuart32_serial_setbrg()
310 sc_pm_clock_rate_t rate = 80000000; in bl31_early_platform_setup2() local
311 sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/imx/imx8qm/
H A Dimx8qm_bl31_setup.c95 unsigned int diff1, diff2, tmp, rate; in lpuart32_serial_setbrg() local
100 sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); in lpuart32_serial_setbrg()
106 tmp_sbr = (rate / (baudrate * tmp_osr)); in lpuart32_serial_setbrg()
111 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate; in lpuart32_serial_setbrg()
112 diff2 = rate / (tmp_osr * (tmp_sbr + 1)); in lpuart32_serial_setbrg()
324 sc_pm_clock_rate_t rate = 80000000; in bl31_early_platform_setup2() local
325 sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/amd/versal2/
H A Dscmi.c25 unsigned long rate; member
35 .rate = (_rate), \
306 *array = clock->rate; in plat_scmi_clock_rates_array()
325 VERBOSE("SCMI: CLK: id: %d, get_rate: %lu\n", scmi_id, clock->rate); in plat_scmi_clock_get_rate()
326 ret = clock->rate; in plat_scmi_clock_get_rate()
332 unsigned long rate) in plat_scmi_clock_set_rate() argument
340 VERBOSE("SCMI: CLK: id: %d, set_rate: %lu\n", scmi_id, rate); in plat_scmi_clock_set_rate()
341 clock->rate = rate; in plat_scmi_clock_set_rate()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp_clkfunc.h31 void stm32mp_stgen_config(unsigned long rate);
/rk3399_ARM-atf/plat/imx/common/
H A Dimx_sip_handler.c75 sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq; in imx_cpufreq_set_target() local
78 sc_pm_set_clock_rate(ipc_handle, ap_cluster_index[cluster_id], SC_PM_CLK_CPU, &rate); in imx_cpufreq_set_target()
81 sc_pm_set_clock_rate(ipc_handle, SC_R_A35, SC_PM_CLK_CPU, &rate); in imx_cpufreq_set_target()
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/ls1046ardb/
H A Dddr_init.c159 unsigned long rate; member
176 if (table[i].rate >= clk) { in board_static_ddr()
181 VERBOSE("Found static setting for rate %ld\n", table[i].rate); in board_static_ddr()
/rk3399_ARM-atf/plat/imx/common/sci/svc/pm/
H A Dpm_rpc_clnt.c236 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) in sc_pm_set_clock_rate() argument
244 RPC_U32(&msg, 0U) = *(uint32_t *)rate; in sc_pm_set_clock_rate()
251 *rate = RPC_U32(&msg, 0U); in sc_pm_set_clock_rate()
257 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) in sc_pm_get_clock_rate() argument
271 if (rate != NULL) { in sc_pm_get_clock_rate()
272 *rate = RPC_U32(&msg, 0U); in sc_pm_get_clock_rate()
/rk3399_ARM-atf/plat/imx/common/include/sci/svc/pm/
H A Dsci_pm_api.h454 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
475 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);

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