| #
5cc5ded8 |
| 06-Aug-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(ast2700): fix mpll calculate statement" into integration
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| #
aa096222 |
| 09-Jul-2024 |
Kevin Chen <kevin_chen@aspeedtech.com> |
fix(ast2700): fix mpll calculate statement
pll_reg.b.bypass equal to 1U, bypass the mpll calculating
pll_reg.b.bypass equal to 0U, need to calculate mpll
Change-Id: I6cace1509d9429a97c7c9481dc1e2e4
fix(ast2700): fix mpll calculate statement
pll_reg.b.bypass equal to 1U, bypass the mpll calculating
pll_reg.b.bypass equal to 0U, need to calculate mpll
Change-Id: I6cace1509d9429a97c7c9481dc1e2e4f95134d6c
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
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| #
fc189d95 |
| 02-Jul-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(ast2700): set up CPU clock frequency by SCU" into integration
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| #
e3d1bbdb |
| 18-Jun-2024 |
Kevin Chen <kevin_chen@aspeedtech.com> |
feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[
feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL
2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL
Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
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| #
58f00553 |
| 30-Oct-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(ast2700): add device mapping for coherent memory" into integration
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| #
cef2e925 |
| 30-Oct-2023 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
fix(ast2700): add device mapping for coherent memory
The coherent memory should be mapped as Device nGnRnE.
This fix adds the missing MMU attributes for coherent memory
if enabled.
Signed-off-by: C
fix(ast2700): add device mapping for coherent memory
The coherent memory should be mapped as Device nGnRnE.
This fix adds the missing MMU attributes for coherent memory
if enabled.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I90b8de167c48f03392c9740f88f4b1e7b073a82d
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| #
f80323da |
| 29-Sep-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "refactor(ast2700): adopt RESET_TO_BL31 boot flow" into integration
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| #
564e073c |
| 27-Sep-2023 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
refactor(ast2700): adopt RESET_TO_BL31 boot flow
Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initializat
refactor(ast2700): adopt RESET_TO_BL31 boot flow
Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initialization are moved to a preceding MCU.
This patch updates the build configuration and also adds
the SMP mailbox setup code to hold secondary cores until
they are being waken up.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18
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| #
032c6983 |
| 15-Jun-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(ast2700): add Aspeed AST2700 platform support" into integration
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| #
85f199b7 |
| 02-Nov-2022 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
feat(ast2700): add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the doc
feat(ast2700): add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.
Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
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