198 	unsigned int rate;  member
258 	.rate = _rate##U,						\
371 static int clk_scmi_cci_set_rate(rk_scmi_clock_t *clock, unsigned long rate);
380 		if (freq_hz == table[i].rate)  in rkclk_get_pvtpll_config()
400 static int clk_cpul_set_rate(unsigned long rate, enum pll_type_sel type)  in clk_cpul_set_rate()  argument
405 	if (rate == 0)  in clk_cpul_set_rate()
409 					 sys_clk_info.cpul_rate_count, rate);  in clk_cpul_set_rate()
458 	div = DIV_ROUND_UP(GPLL_RATE, rate) - 1;  in clk_cpul_set_rate()
471 static int clk_scmi_cpul_set_rate(rk_scmi_clock_t *clock, unsigned long rate)  in clk_scmi_cpul_set_rate()  argument
475 	if (rate == 0)  in clk_scmi_cpul_set_rate()
478 	ret = clk_cpul_set_rate(rate, PLL_SEL_AUTO);  in clk_scmi_cpul_set_rate()
480 		sys_clk_info.cpul_rate = rate;  in clk_scmi_cpul_set_rate()
481 		ret = clk_scmi_cci_set_rate(clock, rate / 2);  in clk_scmi_cpul_set_rate()
562 static int clk_cpub_set_rate(unsigned long rate, enum pll_type_sel type)  in clk_cpub_set_rate()  argument
567 	if (rate == 0)  in clk_cpub_set_rate()
571 					 sys_clk_info.cpub_rate_count, rate);  in clk_cpub_set_rate()
622 	div = DIV_ROUND_UP(GPLL_RATE, rate) - 1;  in clk_cpub_set_rate()
635 static int clk_scmi_cpub_set_rate(rk_scmi_clock_t *clock, unsigned long rate)  in clk_scmi_cpub_set_rate()  argument
639 	if (rate == 0)  in clk_scmi_cpub_set_rate()
642 	if ((rate & OPP_LENGTH_LOW) != 0) {  in clk_scmi_cpub_set_rate()
648 	ret = clk_cpub_set_rate(rate, PLL_SEL_AUTO);  in clk_scmi_cpub_set_rate()
650 		sys_clk_info.cpub_rate = rate;  in clk_scmi_cpub_set_rate()
757 static int clk_cci_set_rate(unsigned long rate, enum pll_type_sel type)  in clk_cci_set_rate()  argument
762 	if (rate == 0)  in clk_cci_set_rate()
766 					 sys_clk_info.cci_rate_count, rate);  in clk_cci_set_rate()
792 		sys_clk_info.cci_rate = rate;  in clk_cci_set_rate()
806 static int clk_scmi_cci_set_rate(rk_scmi_clock_t *clock, unsigned long rate)  in clk_scmi_cci_set_rate()  argument
808 	if (rate == 0)  in clk_scmi_cci_set_rate()
811 	return clk_cci_set_rate(rate, PLL_SEL_AUTO);  in clk_scmi_cci_set_rate()
849 static int clk_gpu_set_rate(unsigned long rate, enum pll_type_sel type)  in clk_gpu_set_rate()  argument
855 					 sys_clk_info.gpu_rate_count, rate);  in clk_gpu_set_rate()
881 	div = DIV_ROUND_UP(GPLL_RATE, rate);  in clk_gpu_set_rate()
893 static int clk_scmi_gpu_set_rate(rk_scmi_clock_t *clock, unsigned long rate)  in clk_scmi_gpu_set_rate()  argument
897 	if (rate == 0)  in clk_scmi_gpu_set_rate()
900 	if ((rate & OPP_LENGTH_LOW) != 0) {  in clk_scmi_gpu_set_rate()
906 	ret = clk_gpu_set_rate(rate, PLL_SEL_AUTO);  in clk_scmi_gpu_set_rate()
908 		sys_clk_info.gpu_rate = rate;  in clk_scmi_gpu_set_rate()
949 static int clk_npu_set_rate(unsigned long rate, enum pll_type_sel type)  in clk_npu_set_rate()  argument
955 					 sys_clk_info.npu_rate_count, rate);  in clk_npu_set_rate()
983 	div = DIV_ROUND_UP(GPLL_RATE, rate);  in clk_npu_set_rate()
997 static int clk_scmi_npu_set_rate(rk_scmi_clock_t *clock, unsigned long rate)  in clk_scmi_npu_set_rate()  argument
1001 	if (rate == 0)  in clk_scmi_npu_set_rate()
1004 	if ((rate & OPP_LENGTH_LOW) != 0) {  in clk_scmi_npu_set_rate()
1010 	ret = clk_npu_set_rate(rate, PLL_SEL_AUTO);  in clk_scmi_npu_set_rate()
1012 		sys_clk_info.npu_rate = rate;  in clk_scmi_npu_set_rate()
1220 int rockchip_opteed_clk_set_rate(uint64_t clk_idx, uint64_t rate)  in rockchip_opteed_clk_set_rate()  argument
1225 		INFO("%s: clk-%ld, %ld not supported\n", __func__, clk_idx, rate);  in rockchip_opteed_clk_set_rate()
1231 		table->clk_ops->set_rate(table, rate);  in rockchip_opteed_clk_set_rate()
1236 int rockchip_opteed_clk_get_rate(uint64_t clk_idx, uint64_t *rate)  in rockchip_opteed_clk_get_rate()  argument
1247 		*rate = (uint64_t)table->clk_ops->get_rate(table);  in rockchip_opteed_clk_get_rate()