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Searched refs:mmio_setbits_32 (Results 1 – 25 of 192) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spmc/
H A Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
101 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(1)); in spmc_init()
[all …]
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dplat_pm.c271 mmio_setbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); in a3700_pwr_domain_on()
304 mmio_setbits_32(MVEBU_PM_NB_CPU_PWR_CTRL_REG, MVEBU_PM_L2_FLUSH_EN); in a3700_set_gen_pwr_off_option()
330 mmio_setbits_32(MVEBU_PM_NB_PWR_DEBUG_REG, MVEBU_PM_IGNORE_CM3_SLEEP); in a3700_set_gen_pwr_off_option()
331 mmio_setbits_32(MVEBU_PM_NB_PWR_DEBUG_REG, MVEBU_PM_IGNORE_CM3_DEEP); in a3700_set_gen_pwr_off_option()
337 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_NB_SRAM_LKG_PD_EN); in a3700_set_gen_pwr_off_option()
346 mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_INTERFACE_IDLE); in a3700_set_gen_pwr_off_option()
349 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
350 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
355 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_SOC_PD); in a3700_set_gen_pwr_off_option()
356 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_SOC_PD); in a3700_set_gen_pwr_off_option()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spmc/
H A Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
105 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in spmc_init()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/
H A Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
53 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
98 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
100 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
101 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
102 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
103 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
104 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
110 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in spmc_init()
[all …]
/rk3399_ARM-atf/plat/brcm/board/stingray/driver/
H A Dusb_phy.c75 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO); in u2_phy_ext_fsm_power_on()
79 mmio_setbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq); in u2_phy_ext_fsm_power_on()
95 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_CTRL_CORERDY); in u2_phy_ext_fsm_power_on()
99 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_BG_PWRDWNB); in u2_phy_ext_fsm_power_on()
103 mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_onin); in u2_phy_ext_fsm_power_on()
104 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_LDO_PWRDWNB); in u2_phy_ext_fsm_power_on()
108 mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_okin); in u2_phy_ext_fsm_power_on()
112 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_PLL_PWRDWNB); in u2_phy_ext_fsm_power_on()
123 mmio_setbits_32(u2_phy->pll_ctrl_reg, USB2_PLL_RESETB); in u2_phy_ext_fsm_power_on()
124 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_RESETB); in u2_phy_ext_fsm_power_on()
[all …]
H A Dusb.c26 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_PM_RESET_N_R); in usb_pm_rescal_init()
28 mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, RESCAL_I_RSTB); in usb_pm_rescal_init()
31 mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, in usb_pm_rescal_init()
63 mmio_setbits_32(USB3H_U3PHY_CTRL, PHY_RESET); in usb3h_usb2drd_init()
70 mmio_setbits_32(USB3H_U3PHY_CTRL, MDIO_RESET); in usb3h_usb2drd_init()
116 mmio_setbits_32(DRDU3_U3PHY_CTRL, PHY_RESET); in usb3drd_init()
123 mmio_setbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET); in usb3drd_init()
176 mmio_setbits_32(USB3H_SOFT_RESET_CTRL, in usb_enable_coherence()
178 mmio_setbits_32(DRDU2_SOFT_RESET_CTRL, in usb_enable_coherence()
180 mmio_setbits_32(USB3H_U3PHY_CTRL, USB3H_U3SOFT_RST_N); in usb_enable_coherence()
[all …]
/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Ddram.c231 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_143, 0xF << 24); in dram_lp_auto_disable()
282 mmio_setbits_32(IMX_PCC5_BASE + 0x108, 0x2 << 22); in dram_enter_self_refresh()
284 mmio_setbits_32(IMX_PCC5_BASE + 0x108, (BIT(30) | BIT(28))); in dram_enter_self_refresh()
292 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in dram_enter_self_refresh()
308 mmio_setbits_32(IMX_LPAV_SIM_BASE + LPDDR_CTRL2, LPDDR_EN_CLKGATE); in dram_enter_self_refresh()
325 mmio_setbits_32(IMX_PCC5_BASE + 0x108, 0x2 << 22); in dram_enter_retention()
333 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in dram_enter_retention()
414 mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(30)); in dram_exit_retention()
417 mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(28)); in dram_exit_retention()
442 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_137, 0x1); in dram_exit_retention()
[all …]
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dbl31_setup.c85 mmio_setbits_32(DMAC_M0_IDM_IO_CONTROL_DIRECT, BOOT_MANAGER_NS); in brcm_stingray_dma_pl330_init()
100 mmio_setbits_32(DMAC_M0_IDM_RESET_CONTROL, 0x1); in brcm_stingray_dma_pl330_init()
115 mmio_setbits_32(idm_reset_control, 0x1); in brcm_stingray_spi_pl022_init()
211 mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL, in brcm_stingray_sata_init()
215 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_SATA_RESET_N); in brcm_stingray_sata_init()
223 mmio_setbits_32(SATA_APBT_IDM_PORT_REG(sata_port, in brcm_stingray_sata_init()
230 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
232 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
234 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
236 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
[all …]
H A Dihost_pm.c152 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, rst); in ihost_power_on_cluster()
178 mmio_setbits_32(CRMU_BISR_PDG_MASK, (1 << bisr)); in ihost_power_on_cluster()
233 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
252 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_MODE_CONTROL, in ihost_power_on_cluster()
256 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_0, in ihost_power_on_cluster()
263 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_1, in ihost_power_on_cluster()
268 mmio_setbits_32(CDRU_CCN_REGISTER_CONTROL_1, d2xs); in ihost_power_on_cluster()
287 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
295 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_1, in ihost_power_on_cluster()
299 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_reset_manager.c96 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask); in config_hps_hs_before_warm_reset()
261 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
272 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
287 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_reset()
312 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), in socfpga_bridges_reset()
315 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
332 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), in socfpga_bridges_reset()
353 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_reset()
361 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), in socfpga_bridges_reset()
382 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), in socfpga_bridges_reset()
[all …]
/rk3399_ARM-atf/plat/allwinner/common/
H A Dsunxi_cpu_ops.c67 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), in sunxi_cpu_off()
79 mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(1)); in sunxi_cpu_off()
101 mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster), in sunxi_cpu_on()
108 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on()
110 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on()
112 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_on()
120 mmio_setbits_32(SUNXI_CPU_CTRL_REG(core), BIT(0)); in sunxi_cpu_on()
128 mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(0)); in sunxi_cpu_on()
130 mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0)); in sunxi_cpu_on()
132 mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8)); in sunxi_cpu_on()
/rk3399_ARM-atf/plat/imx/imx8m/
H A Dgpc_common.c56 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_off()
61 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
76 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
78 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); in imx_set_cpu_pwr_on()
87 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
96 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
99 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
120 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
121 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
124 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dbl31_plat_setup.c42 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, in platform_setup_cpu()
44 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, in platform_setup_cpu()
46 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, in platform_setup_cpu()
57 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
65 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
71 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, in platform_setup_cpu()
78 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, in platform_setup_cpu()
81 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, in platform_setup_cpu()
/rk3399_ARM-atf/plat/mediatek/drivers/rng/mt8188/
H A Drng_plat.c25 mmio_setbits_32(TRNG_SWRST_SET_REG, RNG_SWRST_B); in trng_external_swrst()
26 mmio_setbits_32(TRNG_SWRST_CLR_REG, RNG_SWRST_B); in trng_external_swrst()
33 mmio_setbits_32(RNG_EN, DRBG_EN | NRBG_EN); in trng_external_swrst()
46 mmio_setbits_32(RNG_SWRST, SWRST_B); in get_entropy_32()
48 mmio_setbits_32(RNG_EN, DRBG_EN | NRBG_EN); in get_entropy_32()
85 mmio_setbits_32(RNG_EN, DRBG_EN | NRBG_EN); in plat_get_entropy()
/rk3399_ARM-atf/plat/mediatek/mt8173/
H A Dbl31_plat_setup.c40 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); in platform_setup_cpu()
41 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, in platform_setup_cpu()
47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, in platform_setup_cpu()
51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, in platform_setup_cpu()
55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, in platform_setup_cpu()
59 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
61 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
/rk3399_ARM-atf/plat/mediatek/drivers/mtcmos/
H A Dmtcmos.c85 mmio_setbits_32(reg, SRAM_PDN); in spm_mtcmos_ctrl()
91 mmio_setbits_32(reg, RTFF_CLK_DIS); in spm_mtcmos_ctrl()
92 mmio_setbits_32(reg, RTFF_SAVE); in spm_mtcmos_ctrl()
96 mmio_setbits_32(reg, RTFF_SAVE_FLAG); in spm_mtcmos_ctrl()
101 mmio_setbits_32(reg, PWR_ISO); in spm_mtcmos_ctrl()
102 mmio_setbits_32(reg, PWR_CLK_DIS); in spm_mtcmos_ctrl()
115 mmio_setbits_32(reg, PWR_ON); in spm_mtcmos_ctrl()
122 mmio_setbits_32(reg, PWR_ON_2ND); in spm_mtcmos_ctrl()
130 mmio_setbits_32(reg, PWR_RST_B); in spm_mtcmos_ctrl()
134 mmio_setbits_32(reg, RTFF_CLK_DIS); in spm_mtcmos_ctrl()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spmc/
H A Dmtspmc.c52 mmio_setbits_32(reg, SW_NO_WAIT_Q); in spm_disable_cpu_auto_off()
115 mmio_setbits_32(reg, (arm64 & 1) << (i + cpu)); in mcucfg_init_archstate()
175 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
176 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
177 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
181 mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
189 mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
190 mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
191 mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
192 mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Dlpddr4_dvfs.c28 mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); in lpddr4_mr_write()
122 mmio_setbits_32(DDRC_ZQCTL0(0), BIT(31)); in lpddr4_swffc()
123 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); in lpddr4_swffc()
124 mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31)); in lpddr4_swffc()
136 mmio_setbits_32(DDRC_PWRCTL(0), 0x60); in lpddr4_swffc()
144 mmio_setbits_32(DDRC_DBG1(0), 0x1); in lpddr4_swffc()
212 mmio_setbits_32(DDRC_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
214 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
216 mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
236 mmio_setbits_32(DDRC_DBGCMD(0), 0x10); in lpddr4_swffc()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_power.c59 mmio_setbits_32(APUSYS_PCU + APU_PCUTOP_CTRL_SET, PMIC_IRQ_EN); in buck_off_by_pcu()
77 mmio_setbits_32(APUSYS_AO_CTL + APUSYS_AO_SRAM_SET, BIT(10)); in apu_buck_off_cfg()
78 mmio_setbits_32(APUSYS_AO_CTL + APUSYS_AO_SRAM_CLR, BIT(9)); in apu_buck_off_cfg()
79 mmio_setbits_32(APUSYS_AO_CTL + APUSYS_AO_SRAM_CLR, BIT(12)); in apu_buck_off_cfg()
80 mmio_setbits_32(APUSYS_AO_CTL + APUSYS_AO_SRAM_CLR, BIT(14)); in apu_buck_off_cfg()
109 mmio_setbits_32(APUSYS_AO_CTL + APUSYS_AO_SRAM_SET, BIT(6)); in apu_buck_off_cfg()
111 mmio_setbits_32(APUSYS_AO_CTL + APUSYS_AO_SRAM_SET, BIT(7)); in apu_buck_off_cfg()
166 mmio_setbits_32(APUSYS_BASE + APU_ARE, ARE_RCX_AO_EN); in apu_pll_init()
167 mmio_setbits_32(APUSYS_BASE + APU_ARE_REG, ARE_RCX_AO_EN); in apu_pll_init()
202 mmio_setbits_32(APUSYS_BASE + APU_ARE, ARE_VCORE_EN); in apu_are_init()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/dfd/mt8188/
H A Dplat_dfd.c24 mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); in dfd_setup()
26 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); in dfd_setup()
27 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); in dfd_setup()
28 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); in dfd_setup()
29 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
71 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
/rk3399_ARM-atf/plat/arm/board/morello/
H A Dmorello_bl2_setup.c95 mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2); in dmc_ecc_setup()
96 mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2); in dmc_ecc_setup()
101 mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4); in dmc_ecc_setup()
102 mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4); in dmc_ecc_setup()
115 mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL, in dmc_ecc_setup()
117 mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL, in dmc_ecc_setup()
130 mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG, in dmc_ecc_setup()
132 mmio_setbits_32(MORELLO_DMC1_ERR0CTLR0_REG, in dmc_ecc_setup()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm_cpc.c153 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_PROF_EN); in mtk_cpc_config()
160 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_AUTO_OFF_EN); in mtk_cpc_config()
163 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_AUTO_OFF_EN); in mtk_cpc_config()
242 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, (CPC_DBG_EN | CPC_CALC_EN)); in mtk_cpc_init()
249 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, (CPC_OFF_PRE_EN | in mtk_cpc_init()
255 mmio_setbits_32(MCSIC_DCM0, 0xFFFF); in mtk_cpc_init()
256 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in mtk_cpc_init()
258 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in mtk_cpc_init()
259 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, SSPM_CORE_PWR_ON_EN); in mtk_cpc_init()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/
H A Dgpc.c143 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
165 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
177 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
211 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
221 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
229 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
273 mmio_setbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); in imx_gpc_pm_domain_enable()
275 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
283 mmio_setbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); in imx_gpc_pm_domain_enable()
285 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dfd/
H A Dplat_dfd.c29 mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); in dfd_setup()
36 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); in dfd_setup()
46 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); in dfd_setup()
52 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); in dfd_setup()
55 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
115 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
/rk3399_ARM-atf/drivers/brcm/
H A Dsotp.c80 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
89 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
98 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_read()
121 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_read()
172 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
181 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
204 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
213 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_write()
237 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
245 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_write()

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