Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinne

Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinner): add extra CPU control registers
refactor(allwinner): consolidate sunxi_cfg.h files

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feat(allwinner): add support for Allwinner T507 SoC

The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision

feat(allwinner): add support for Allwinner T507 SoC

The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision out there, which uses a different CPU cluster control block.
The same die revision has been spotted in some, but not all, H313 SoCs.

Apart from that IP block, the rest of the SoC seems the same, so we can
support them using the existing H616 port. The die revision can be
auto-detected, so there is no extra build option or knowledge needed.

Provide the deviating CPU power up/down sequence for the die variant.
The new IP block uses per-core instead of per-cluster registers, but
follows the same pattern otherwise.

Since the CPU ops code is shared among all Allwinner SoCs, we need to
dummy-define the new register names for the older SoCs. The actual new
code is guarded by a predicate function, that is hard coded to return
true on the other SoCs. Since this is a static inline function in a
header file, the compiler will optimise away the unneeded branch there,
so the generated code for the other SoCs stays the same.

Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "allwinner-r329" into integration

* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow

Merge changes from topic "allwinner-r329" into integration

* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow new AA64nAA32 position
fix(plat/allwinner): delay after enabling CPU power

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refactor(plat/allwinner): allow new AA64nAA32 position

In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Clus

refactor(plat/allwinner): allow new AA64nAA32 position

In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.

Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.

Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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fix(plat/allwinner): delay after enabling CPU power

Adds a 1us delay after enabling power to a CPU core, to prevent
inrush-caused CPU crash before it's up.

Change-Id: I8f4c1b0dc0d1d976b31ddc30efe7a

fix(plat/allwinner): delay after enabling CPU power

Adds a 1us delay after enabling power to a CPU core, to prevent
inrush-caused CPU crash before it's up.

Change-Id: I8f4c1b0dc0d1d976b31ddc30efe7a77a1619b1b3
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
all

Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
allwinner: Express memmap more dynamically
allwinner: Move sunxi_cpu_power_off_self() into platforms
allwinner: Move SEPARATE_NOBITS_REGION to platforms
doc: allwinner: Reorder sections, document memory mapping

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allwinner: Move sunxi_cpu_power_off_self() into platforms

The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new pl

allwinner: Move sunxi_cpu_power_off_self() into platforms

The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new platforms easier, move sunxi_cpu_power_off_self()
into the SoC directory, so we don't need to carry definitions for both
methods for all SoCs.

On the H6 we just need to trigger the CPUIDLE hardware, so can get rid
of all the code to program the ARISC, which is now only needed for the
A64 version.

Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "allwinner: Use CPUIDLE hardware when available" into integration

allwinner: Use CPUIDLE hardware when available

This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.

Change-Id: I9f2fed597189bb387de7

allwinner: Use CPUIDLE hardware when available

This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.

Change-Id: I9f2fed597189bb387de79e8e76a7da3375e1ee91
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "sunxi-split-psci" into integration

* changes:
allwinner: Split native and SCPI-based PSCI implementations
allwinner: psci: Improve system shutdown/reset sequence
allw

Merge changes from topic "sunxi-split-psci" into integration

* changes:
allwinner: Split native and SCPI-based PSCI implementations
allwinner: psci: Improve system shutdown/reset sequence
allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback
allwinner: Separate code to power off self and other CPUs

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allwinner: Separate code to power off self and other CPUs

Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.

allwinner: Separate code to power off self and other CPUs

Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.
This actually simplifies things, because all callers either operate on
the local CPU only (sunxi_pwr_down_wfi()) or other CPUs only
(sunxi_cpu_power_off_others()). This avoids needing a second MPIDR read
to choose the appropriate code path.

Change-Id: I55de85025235cc95466bfa106831fc4c2368f527
Signed-off-by: Samuel Holland <samuel@sholland.org>

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Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration

allwinner: Fix incorrect ARISC code patch offset check

The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
th

allwinner: Fix incorrect ARISC code patch offset check

The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
the parameter is unnecessary. Instead of adding more code to fix the
check, remove the parameter to avoid the problem entirely.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6

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Merge pull request #1826 from smaeul/allwinner

allwinner: A few minor improvements

allwinner: Clean up CPU ops functions

Convert them to take an mpidr instead of a (cluster, core) pair. This
simplifies all of the call sites, and actually makes the functions a bit
smaller.

Signed-

allwinner: Clean up CPU ops functions

Convert them to take an mpidr instead of a (cluster, core) pair. This
simplifies all of the call sites, and actually makes the functions a bit
smaller.

Signed-off-by: Samuel Holland <samuel@sholland.org>

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2

Allwinner/pmic v2

allwinner: Use the arisc to turn off ARM cores

PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a co

allwinner: Use the arisc to turn off ARM cores

PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a core into WFI on CPU_OFF right now.
To fix this let's task the "arisc" management processor (an OpenRISC
core) with that task of asserting reset and turning off the core's power
domain. We use a handcrafted sequence of OpenRISC instructions to
achieve this, and hand this data over to the new sunxi_execute_arisc_code()
routine.
The commented source code for this routine is provided in a separate file,
but the ATF code contains the already encoded instructions as data.
The H6 uses the same algorithm, but differs in the MMIO addresses, so
provide a SoC (family) specific copy of that code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Export sunxi_private.h

So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will

allwinner: Export sunxi_private.h

So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will need some of those in the platform specific code
parts as well, and want to introduce new functions shared across the
whole platform port.

So move the sunxi_private.h file into the common/include directory, so
that it becomes visible to all parts of the platform code.
Fix up the existing #includes and add missing ones, also add the
sunxi_read_soc_id() prototype here.

This will be used in follow up patches.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge pull request #1458 from Andre-ARM/allwinner/fixes

allwinner: various smaller fixes

allwinner: cpu-ops: avoid PSCI on/off output

The "INFO" output in sunxi_cpu_ops.c is quite verbose, so make this more
obvious by changing the log level to "VERBOSE" and so avoiding it to
be printed

allwinner: cpu-ops: avoid PSCI on/off output

The "INFO" output in sunxi_cpu_ops.c is quite verbose, so make this more
obvious by changing the log level to "VERBOSE" and so avoiding it to
be printed in a normal (even debug) build.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge pull request #1400 from Andre-ARM/allwinner/v1

Allwinner platform support

allwinner: Add functions to control CPU power/reset

sun50i_cpu_on will be used by the PSCI implementation to initialize
secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by
PSCI d

allwinner: Add functions to control CPU power/reset

sun50i_cpu_on will be used by the PSCI implementation to initialize
secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by
PSCI directly, because it is not possible for a CPU to use this function
to power itself down. Power cannot be shut off until the outputs are
clamped, and MMIO does not work once the outputs are clamped.

But at least CPU0 can shutdown the other cores early in the BL31 boot
process and before shutting down the system.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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