Merge "fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor" into integration

fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor

Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via th

fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor

Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via the Cortex-M3 secure
coprocessor.

Recall that Turris MOX has a HW bug wherein a SoC reset initiated by
writing the magic value to the North Bridge Warm Reset register may
randomly freeze the board.

Back in 2021 we introduced the CM3_SYSTEM_RESET build option for the
Armada 3700 platform, which, when enabled, adds code to the PSCI reset
handler so that the SoC reset is done by requesting the firmware in the
Cortex-M3 secure coprocessor to do it, instead of writing the Warm Reset
register.

The secure coprocessor firmware tried various things to put the board
into a state where the SoC reset circuit would work correctly. This
managed to fix the issue for some boards, but not for all of them.

Another considered method to overcome this issue was to reset all the
SoC peripheral controllers one by one by writing to specific registers,
instead of triggering the SoC reset circuit via the Warm Reset register.
This method was not used because until now, there was one peripheral
that I could not find a way how to reset properly: the Generic Interrupt
Controller (GIC).

After 3 years I have finally found a way how to reset the GIC, and it
needs to be done by the main processor, before the secure coprocessor
resets the main processor.

Change-Id: Icc23251ef97738b6b48af514d5118440ec21cdd7
Signed-off-by: Marek Behún <marek.behun@nic.cz>

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Merge "plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC" into integration

plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC

This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src c

plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC

This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src configuration.

By default this new option is disabled as it is board specific and no
other A37xx board has PM wake up src configuration.

Currently neither upstream U-Boot nor upstream Linux kernel has wakeup
support for A37xx platforms, so having it disabled does not cause any
issue.

Prior this commit PM wake up src configuration specific for Armada 3720
Development Board was enabled for every A37xx board. After this change it
is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766

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Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration

plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor

Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset h

plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor

Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset handler to try to do system
reset by the WTMI firmware running on the Cortex-M3 secure coprocessor.
(This function is exposed via the mailbox interface.)

The reason is that the Turris MOX board has a HW bug which causes reset
to hang unpredictably. This issue can be solved by putting the board in
a specific state before reset.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f

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Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration

* changes:
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
drivers: marvell: add support for mapping th

Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration

* changes:
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
drivers: marvell: add support for mapping the entire LLC to SRAM
plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms
plat: marvell: armada: reduce memory size reserved for FIP image
plat: marvell: armada: platform definitions cleanup
plat: marvell: armada: a8k: check CCU window state before loading MSS BL2
drivers: marvell: add CCU driver API for window state checking
drivers: marvell: align and extend llc macros
plat: marvell: a8k: move address config of cp1/2 to BL2
plat: marvell: armada: re-enable BL32_BASE definition
plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer
marvell: comphy: initialize common phy selector for AP mode
marvell: comphy: update rx_training procedure
plat: marvell: armada: configure amb for all CPs
plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs

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plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs

The Marvell Armada 37xx SoCs-based platforms contain a bit
awkward directory structure because the currently only one
supported PLAT and

plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs

The Marvell Armada 37xx SoCs-based platforms contain a bit
awkward directory structure because the currently only one
supported PLAT and PLAT_FAMILY are the same. Modify the latter
to 'a3k' in order to improve it and keep plat/marvell/armada
tree more consistent:

plat/marvell/
├── armada
│   ├── a3k
│   │   ├── a3700

[...]

│   ├── a8k
│   │   ├── a70x0

[...]

Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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