Lines Matching refs:mmio_setbits_32
231 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_143, 0xF << 24); in dram_lp_auto_disable()
282 mmio_setbits_32(IMX_PCC5_BASE + 0x108, 0x2 << 22); in dram_enter_self_refresh()
284 mmio_setbits_32(IMX_PCC5_BASE + 0x108, (BIT(30) | BIT(28))); in dram_enter_self_refresh()
292 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in dram_enter_self_refresh()
308 mmio_setbits_32(IMX_LPAV_SIM_BASE + LPDDR_CTRL2, LPDDR_EN_CLKGATE); in dram_enter_self_refresh()
325 mmio_setbits_32(IMX_PCC5_BASE + 0x108, 0x2 << 22); in dram_enter_retention()
333 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in dram_enter_retention()
414 mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(30)); in dram_exit_retention()
417 mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(28)); in dram_exit_retention()
442 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_137, 0x1); in dram_exit_retention()
444 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_132, 0x01000000); in dram_exit_retention()
450 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_174, 0x03030000); in dram_exit_retention()
452 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_175, 0x03); in dram_exit_retention()
454 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_191, 0x03030000); in dram_exit_retention()
456 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_192, 0x03); in dram_exit_retention()
458 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_212, 0x300); in dram_exit_retention()
460 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_214, 0x03000000); in dram_exit_retention()
462 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_217, 0x300); in dram_exit_retention()
464 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_181, 0x03030000); in dram_exit_retention()
469 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_182, 0x03030303); in dram_exit_retention()
471 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_134, 0x000F0000); in dram_exit_retention()
474 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_137, 0x1); in dram_exit_retention()
476 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_132, 0x01000000); in dram_exit_retention()
482 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_174, 0x00030000); in dram_exit_retention()
484 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_191, 0x00030000); in dram_exit_retention()
486 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_181, 0x03030000); in dram_exit_retention()
488 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_134, 0x000F0000); in dram_exit_retention()
541 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_52, 0x10000); /* CALVL */ in dram_exit_retention()
542 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_26, 0x100); /* WRLVL */ in dram_exit_retention()
543 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_33, 0x10000); /* RDGATE */ in dram_exit_retention()
544 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_33, 0x100); /* RDQLVL */ in dram_exit_retention()
545 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_65, 0x10000); /* WDQLVL */ in dram_exit_retention()
552 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_52, 0x10000); /* CALVL */ in dram_exit_retention()
553 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_26, 0x100); /* WRLVL */ in dram_exit_retention()
554 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_33, 0x10000); /* RDGATE */ in dram_exit_retention()
555 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_33, 0x100); /* RDQLVL */ in dram_exit_retention()
608 mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(30)); in set_ddr_clk()
650 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, LPI_WAKEUP_EN); in lpddr4_dfs()
659 mmio_setbits_32(AVD_SIM_LPDDR_CTRL2, LPDDR_EN_CLKGATE); in lpddr4_dfs()
662 mmio_setbits_32(AVD_SIM_LPDDR_CTRL, SOC_FREQ_REQ); in lpddr4_dfs()