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Searched refs:mask (Results 1 – 25 of 169) sorted by relevance

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/rk3399_ARM-atf/drivers/marvell/comphy/
H A Dphy-comphy-cp110.c116 uint32_t reg, mask, field; in mvebu_cp110_comphy_clr_pipe_selector() local
120 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_clr_pipe_selector()
122 field = reg & mask; in mvebu_cp110_comphy_clr_pipe_selector()
125 reg &= ~mask; in mvebu_cp110_comphy_clr_pipe_selector()
135 uint32_t reg, mask, field; in mvebu_cp110_comphy_clr_phy_selector() local
139 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_clr_phy_selector()
141 field = reg & mask; in mvebu_cp110_comphy_clr_phy_selector()
149 reg &= ~mask; in mvebu_cp110_comphy_clr_phy_selector()
159 uint32_t reg, mask; in mvebu_cp110_comphy_set_phy_selector() local
174 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_set_phy_selector()
[all …]
H A Dphy-comphy-3700.c218 uint16_t mask, bool is_sata) in comphy_set_indirect() argument
235 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); in comphy_set_indirect()
240 uint16_t data, uint16_t mask) in comphy_sata_set_indirect() argument
242 comphy_set_indirect(addr, reg_offset, data, mask, true); in comphy_sata_set_indirect()
247 uint16_t data, uint16_t mask) in comphy_usb3_set_indirect() argument
249 comphy_set_indirect(addr, reg_offset, data, mask, false); in comphy_usb3_set_indirect()
254 uint16_t data, uint16_t mask) in comphy_usb3_set_direct() argument
256 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); in comphy_usb3_set_direct()
374 uint32_t mask, data; in mvebu_a3700_comphy_sgmii_power_on() local
405 mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | in mvebu_a3700_comphy_sgmii_power_on()
[all …]
H A Dphy-comphy-common.h125 uint32_t mask, in polling_with_timeout() argument
134 data = mmio_read_16(addr) & mask; in polling_with_timeout()
136 data = mmio_read_32(addr) & mask; in polling_with_timeout()
145 static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) in reg_set() argument
148 addr, data, mask); in reg_set()
150 mmio_clrsetbits_32(addr, mask, data & mask); in reg_set()
156 uint16_t mask) in reg_set16() argument
160 addr, data, mask); in reg_set16()
162 mmio_clrsetbits_16(addr, mask, data & mask); in reg_set16()
/rk3399_ARM-atf/plat/mediatek/drivers/cirq/
H A Dmt_cirq.c25 int mt_irq_mask_restore(struct mtk_irq_mask *mask) in mt_irq_mask_restore() argument
27 if (mask == NULL) { in mt_irq_mask_restore()
30 if (mask->header != IRQ_MASK_HEADER) { in mt_irq_mask_restore()
33 if (mask->footer != IRQ_MASK_FOOTER) { in mt_irq_mask_restore()
38 mask->mask1); in mt_irq_mask_restore()
40 mask->mask2); in mt_irq_mask_restore()
42 mask->mask3); in mt_irq_mask_restore()
44 mask->mask4); in mt_irq_mask_restore()
46 mask->mask5); in mt_irq_mask_restore()
48 mask->mask6); in mt_irq_mask_restore()
[all …]
/rk3399_ARM-atf/bl32/tsp/
H A Dtsp_context.c124 uint64_t mask; in modify_el1_ctx_regs() local
128 mask = DUMMY_CTX_VALUE; in modify_el1_ctx_regs()
131 mask = DEFAULT_CTX_VALUE; in modify_el1_ctx_regs()
134 modify_el1_common_regs(mask); in modify_el1_ctx_regs()
135 modify_el1_mte2_regs(mask); in modify_el1_ctx_regs()
136 modify_el1_ras_regs(mask); in modify_el1_ctx_regs()
137 modify_el1_s1pie_regs(mask); in modify_el1_ctx_regs()
138 modify_el1_s1poe_regs(mask); in modify_el1_ctx_regs()
139 modify_el1_s2poe_regs(mask); in modify_el1_ctx_regs()
140 modify_el1_tcr2_regs(mask); in modify_el1_ctx_regs()
[all …]
/rk3399_ARM-atf/services/std_svc/trng/
H A Dtrng_main.c25 uint32_t mask = ~0U; in trng_rnd32() local
37 mask >>= 32U - (nbits % 32U); in trng_rnd32()
42 SMC_RET4(handle, TRNG_E_SUCCESS, 0, 0, ent[0] & mask); in trng_rnd32()
45 SMC_RET4(handle, TRNG_E_SUCCESS, 0, (ent[0] >> 32) & mask, in trng_rnd32()
49 SMC_RET4(handle, TRNG_E_SUCCESS, ent[1] & mask, in trng_rnd32()
61 uint64_t mask = ~0ULL; in trng_rnd64() local
74 mask >>= 64U - (nbits % 64U); in trng_rnd64()
79 SMC_RET4(handle, TRNG_E_SUCCESS, 0, 0, ent[0] & mask); in trng_rnd64()
82 SMC_RET4(handle, TRNG_E_SUCCESS, 0, ent[1] & mask, ent[0]); in trng_rnd64()
85 SMC_RET4(handle, TRNG_E_SUCCESS, ent[2] & mask, ent[1], ent[0]); in trng_rnd64()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/
H A Dplat_psci_handlers.c275 uint32_t val, mask; in tegra_reset_all_dma_masters() local
307 mask = GPU_RESET_BIT; in tegra_reset_all_dma_masters()
308 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
311 mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | in tegra_reset_all_dma_masters()
314 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
317 mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | in tegra_reset_all_dma_masters()
321 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
324 mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; in tegra_reset_all_dma_masters()
326 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
329 mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | in tegra_reset_all_dma_masters()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spmc/
H A Dmtspmc.c127 int spm_get_powerstate(uint32_t mask) in spm_get_powerstate() argument
129 return mmio_read_32(SPM_PWR_STATUS) & mask; in spm_get_powerstate()
134 uint32_t mask; in spm_get_cluster_powerstate() local
136 mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP; in spm_get_cluster_powerstate()
138 return spm_get_powerstate(mask); in spm_get_cluster_powerstate()
259 uint32_t mask; in spm_poweroff_cluster() local
266 mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK : in spm_poweroff_cluster()
268 mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask); in spm_poweroff_cluster()
270 while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask) in spm_poweroff_cluster()
278 mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN; in spm_poweroff_cluster()
[all …]
/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dcpuamu.c15 unsigned int mask; member
38 ctx->mask = cpuamu_read_cpuamcntenset_el0(); in cpuamu_context_save()
41 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_save()
60 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_restore()
69 cpuamu_write_cpuamcntenset_el0(ctx->mask); in cpuamu_context_restore()
/rk3399_ARM-atf/lib/locks/exclusive/aarch64/
H A Dspinlock.c135 void bit_lock(bitlock_t *lock, uint8_t mask) in bit_lock() argument
154 : [mask] "r" (mask), [dst] "r" (dst)); in bit_lock()
162 void bit_unlock(bitlock_t *lock, uint8_t mask) in bit_unlock() argument
172 : [mask] "r" (mask), [dst] "r" (dst)); in bit_unlock()
/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_reset_manager.c99 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms) in poll_idle_status() argument
105 if ((mmio_read_32(addr) & mask) == match) { in poll_idle_status()
115 static int poll_idle_status_by_clkcycles(uint32_t addr, uint32_t mask, in poll_idle_status_by_clkcycles() argument
122 if ((mmio_read_32(addr) & mask) == match) { in poll_idle_status_by_clkcycles()
131 static void socfpga_s2f_bridge_mask(uint32_t mask, in socfpga_s2f_bridge_mask() argument
138 if ((mask & SOC2FPGA_MASK) != 0U) { in socfpga_s2f_bridge_mask()
143 if ((mask & LWHPS2FPGA_MASK) != 0U) { in socfpga_s2f_bridge_mask()
149 static void socfpga_f2s_bridge_mask(uint32_t mask, in socfpga_f2s_bridge_mask() argument
167 if ((mask & FPGA2SOC_MASK) != 0U) { in socfpga_f2s_bridge_mask()
170 if ((mask & F2SDRAM0_MASK) != 0U) { in socfpga_f2s_bridge_mask()
[all …]
/rk3399_ARM-atf/include/common/
H A Dpar.h17 uint64_t mask = PAR_ADDR_MASK; in get_par_el1_pa() local
24 mask = PAR_D128_ADDR_MASK; in get_par_el1_pa()
27 return pa & mask; in get_par_el1_pa()
/rk3399_ARM-atf/include/arch/aarch64/
H A Darch_features.h34 #define ISOLATE_FIELD(reg, feat, mask) \ argument
35 ((unsigned int)(((reg) >> (feat)) & mask))
91 #define CREATE_IDREG_UPDATE(name, idreg, idfield, mask, guard, enabled_worlds) \ argument
99 perworld_idregs->idreg &= ~((u_register_t)mask << idfield); \
102 #define CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, guard, \ argument
110 percpu_idregs->idreg &= ~((u_register_t)mask << idfield); \
114 #define CREATE_IDREG_UPDATE(name, idreg, idfield, mask, guard, enabled_worlds) argument
115 #define CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, guard, \ argument
119 #define _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ argument
123 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
[all …]
/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Dmc_rgm.c29 uint32_t current_regs, mask; in mc_rgm_periph_reset() local
34 mask = current_regs ^ value; in mc_rgm_periph_reset()
36 while (mask != 0U) { in mc_rgm_periph_reset()
37 bit_index = __builtin_ffs(mask); in mc_rgm_periph_reset()
62 mask &= ~current_bit_checked; in mc_rgm_periph_reset()
/rk3399_ARM-atf/plat/mediatek/drivers/pmic/mt6363/
H A Dmt6363_psc.c25 static int mt6363_psc_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift) in mt6363_psc_read_field() argument
38 rdata &= (mask << shift); in mt6363_psc_read_field()
44 static int mt6363_psc_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift) in mt6363_psc_write_field() argument
55 org &= ~(mask << shift); in mt6363_psc_write_field()
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/mcdi/
H A Dmtk_mcdi.h18 uint32_t mcdi_avail_cpu_mask_write(uint32_t mask);
19 uint32_t mcdi_avail_cpu_mask_set(uint32_t mask);
20 uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask);
H A Dmtk_mcdi.c48 uint32_t mcdi_avail_cpu_mask_write(uint32_t mask) in mcdi_avail_cpu_mask_write() argument
50 mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, mask); in mcdi_avail_cpu_mask_write()
52 return mask; in mcdi_avail_cpu_mask_write()
55 uint32_t mcdi_avail_cpu_mask_set(uint32_t mask) in mcdi_avail_cpu_mask_set() argument
60 m |= mask; in mcdi_avail_cpu_mask_set()
66 uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask) in mcdi_avail_cpu_mask_clr() argument
71 m &= ~mask; in mcdi_avail_cpu_mask_clr()
/rk3399_ARM-atf/drivers/st/pmic/
H A Dstpmic2.c199 uint8_t register_id, uint8_t value, uint8_t mask) in stpmic2_register_update() argument
209 val = (val & ((uint8_t)~mask)) | (value & mask); in stpmic2_register_update()
212 register_id, value, mask, val); in stpmic2_register_update()
265 uint8_t mask; in stpmic2_regulator_get_voltage() local
271 mask = regul->volt_table_size - 1U; in stpmic2_regulator_get_voltage()
272 if (mask != 0U) { in stpmic2_regulator_get_voltage()
277 value = (value >> regul->volt_shift) & mask; in stpmic2_regulator_get_voltage()
309 uint8_t mask; in stpmic2_regulator_set_voltage() local
315 mask = regul->volt_table_size - 1U; in stpmic2_regulator_set_voltage()
324 mask << regul->volt_shift); in stpmic2_regulator_set_voltage()
[all …]
/rk3399_ARM-atf/plat/imx/common/sci/
H A Dimx8_mu.c46 uint32_t mask = MU_SR_TE0_MASK1 >> regIndex; in MU_SendMessage() local
49 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) in MU_SendMessage()
56 uint32_t mask = MU_SR_RF0_MASK1 >> regIndex; in MU_ReceiveMsg() local
59 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) in MU_ReceiveMsg()
/rk3399_ARM-atf/drivers/nxp/sfp/
H A Dfuse_prov.c24 uint32_t mask) in write_a_fuse() argument
29 if ((last_stored_val & mask) == mask) { in write_a_fuse()
34 sfp_write32(fuse_addr, last_stored_val | (*fuse_hdr_val & mask)); in write_a_fuse()
37 if (sfp_read32(fuse_addr) != (last_stored_val | (*fuse_hdr_val & mask))) { in write_a_fuse()
329 uint32_t mask = 0; in prog_ospr1() local
333 mask = OSPR1_MC_MASK; in prog_ospr1()
337 mask = mask | OSPR1_DBG_LVL_MASK; in prog_ospr1()
340 ret = write_a_fuse(&sfp_ccsr_regs->ospr1, &fuse_hdr->ospr1, mask); in prog_ospr1()
/rk3399_ARM-atf/include/arch/aarch32/
H A Darch_features.h15 #define ISOLATE_FIELD(reg, feat, mask) \ argument
16 ((unsigned int)(((reg) >> (feat)) & mask))
31 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ argument
35 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
39 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \ argument
40 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_ioctl.c208 uint32_t mask, val; in pm_ioctl_sd_dll_reset() local
212 mask = ZYNQMP_SD0_DLL_RST_MASK; in pm_ioctl_sd_dll_reset()
215 mask = ZYNQMP_SD1_DLL_RST_MASK; in pm_ioctl_sd_dll_reset()
224 ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val, flag); in pm_ioctl_sd_dll_reset()
235 ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, 0, flag); in pm_ioctl_sd_dll_reset()
265 uint32_t val, mask; in pm_ioctl_sd_set_tapdelay() local
269 mask = ZYNQMP_SD0_DLL_RST_MASK; in pm_ioctl_sd_set_tapdelay()
272 mask = ZYNQMP_SD1_DLL_RST_MASK; in pm_ioctl_sd_set_tapdelay()
282 if ((val & mask) == 0U) { in pm_ioctl_sd_set_tapdelay()
344 if ((val & mask) == 0) { in pm_ioctl_sd_set_tapdelay()
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_vab.h17 #define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) argument
/rk3399_ARM-atf/plat/mediatek/drivers/mtcmos/
H A Dmtcmos.c35 static int mtcmos_wait_for_state(uint32_t reg, uint32_t mask, bool is_set) in mtcmos_wait_for_state() argument
38 uint32_t expect = is_set ? mask : 0; in mtcmos_wait_for_state()
41 if ((mmio_read_32(reg) & mask) == expect) in mtcmos_wait_for_state()
48 __func__, reg, mask, is_set, mmio_read_32(reg)); in mtcmos_wait_for_state()
59 mmio_write_32(bp_table[i].en_addr, bp_table[i].mask); in spm_mtcmos_ctrl_bus_prot()
61 if (mtcmos_wait_for_state(bp_table[i].rdy_addr, bp_table[i].mask, true)) in spm_mtcmos_ctrl_bus_prot()
/rk3399_ARM-atf/plat/mediatek/drivers/disp/
H A Dmtk_disp_priv.h13 #define DISP_CFG_ENTRY(base_reg, mask) \ argument
14 { .base = (base_reg), .ns_mask = (mask)}

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