Merge changes from topic "a3700-comphy-fixes-1" into integration

* changes:
refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants
refactor(drivers/marvell/comphy-3700):

Merge changes from topic "a3700-comphy-fixes-1" into integration

* changes:
refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants
refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants
refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants
refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants
refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants
refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants
refactor(drivers/marvell/comphy-3700): unify Generation Settings register values
refactor(drivers/marvell/comphy-3700): unify Generation Settings register names
refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes
refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes
refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG
refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition
refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G
refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant
fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics
fix(drivers/marvell/comphy-3700): use reg_set() according to update semantics
fix(drivers/marvell/comphy-3700): fix comments about selector register values
fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register
fix(drivers/marvell/comphy-3700): fix reference clock selection value names
fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant
fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name
fix(drivers/marvell/comphy-3700): fix Generation Setting registers names
fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name

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fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics

Currently reg_set() and reg_set16() are implemented via
mmio_clrsetbits_32(), meaning that first bits from mask are cl

fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics

Currently reg_set() and reg_set16() are implemented via
mmio_clrsetbits_32(), meaning that first bits from mask are cleared,
then data bits are set.

But these function are used everywhere according to update semantics,
where only those bits that are in mask are allowed to be changed.

Example from phy-comphy-cp110.c
mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
/* Set PHY datapath width mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
/* Set Data bus width USB mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
/* Set CORE_CLK output frequency for 250Mhz */
mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);

Change the implementation to update semantics by anding data with mask.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ic72a8f64916274e08baef0b3f4c44a4fa07c1a6c

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Merge "fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode" into integration

fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode

There is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not
SGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z sta

fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode

There is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not
SGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z standard)
but upclocked 2.5x. This mode is commonly known under name 2500Base-X.

So remove incorrect SGMII keyword from names and comments and replace it
by more adequate 2500Base-X keyword.

There is no functional change in code, just renaming macros and updating
comments.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: If79aec16cc233f4896aafd75bfbbebb3f172a197

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Merge pull request #1702 from MISL-EBU-System-SW/patches-18.12

Update code with latest changes from Marvell LSP 18.12

mvebu: cp110: avoid pcie power on/off sequence when called from Linux

In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it c

mvebu: cp110: avoid pcie power on/off sequence when called from Linux

In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it cannot be
executed via GPIO later.
This means that power on can be executed only once, when it's called
from the bootloader.
Power on:
Read bit 21 of the mode, it marks if the caller is
the bootloader or the Linux Kernel.
Power off:
Check if the comphy was already configured to PCIe, if yes,
check if the caller is bootloader, if both conditions are true
(PCIe mode and called by Linux) - skip the power-off.

In addition, fix incorrect documentation describing mode fields -
PCIe width is 3 bits, not 2.

NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work
with it).

Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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Merge pull request #1673 from antonio-nino-diaz-arm/an/headers

Standardise header guards across codebase

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this proje

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1623 from MISL-EBU-System-SW/a3700-support

Add support for Armada 3700 and COMPHY porting layer

mvebu: cp110: introduce COMPHY porting layer

Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length

mvebu: cp110: introduce COMPHY porting layer

Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.

Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h

If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".

The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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