| #
8f64ed92 |
| 30-Oct-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "upstream_deassert_ddr_reset" into integration
* changes: feat(s32g274ardb): add DDR clock source support feat(s32g274ardb): add mc_rgm_release_periph func
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| #
c0cbf5ad |
| 01-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock source and safely deasserting the reset signal for the DDR controller.
These utilities are required before i
feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock source and safely deasserting the reset signal for the DDR controller.
These utilities are required before initializing the DDR subsystem.
Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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| #
f2ab1244 |
| 21-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add mc_rgm_release_periph func
Add `mc_rgm_release_periph` function to allow callers to specify which particular peripheral should be released from reset.
Update the existing `mc
feat(s32g274ardb): add mc_rgm_release_periph func
Add `mc_rgm_release_periph` function to allow callers to specify which particular peripheral should be released from reset.
Update the existing `mc_rgm_release_part` to make use of `mc_rgm_release_periph` function.
Change-Id: Ia2e049ac461f823379ddce34b1406eea0a0a86e9 Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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| #
01c80c19 |
| 09-Oct-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "nxp-clk/add_ddr_clk" into integration
* changes: fix(nxp-clk): function parameter should not be modified feat(nxp-clk): enable the DDR clock feat(nxp-clk): add object
Merge changes from topic "nxp-clk/add_ddr_clk" into integration
* changes: fix(nxp-clk): function parameter should not be modified feat(nxp-clk): enable the DDR clock feat(nxp-clk): add objects needed for DDR clock feat(nxp-clk): setup the DDR PLL feat(nxp-clk): add MC_ME utilities feat(nxp-clk): add partition reset utilities feat(nxp-clk): add partitions objects
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| #
11a7c540 |
| 16-Sep-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(nxp-clk): add partition reset utilities
MC_RGM is a hardware block involved in resetting peripherals and partitions. Here, the accessories for partition reset are added.
Change-Id: If00755fe0e
feat(nxp-clk): add partition reset utilities
MC_RGM is a hardware block involved in resetting peripherals and partitions. Here, the accessories for partition reset are added.
Change-Id: If00755fe0e93ba2e4841f95ed5ae3c87db20bebf Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| #
bccc2275 |
| 27-Sep-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "nxp-s32g274a/err051700" into integration
* changes: feat(s32g274a): enable workaround for ERR051700 fix(s32g274a): workaround for ERR051700 erratum
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| #
b47d085a |
| 12-Sep-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
fix(s32g274a): workaround for ERR051700 erratum
ERR051700 erratum is present on all S32CC-based SoCs and relates to reset. Releasing multiple Software Resettable Domains (SRDs) from reset simultaneo
fix(s32g274a): workaround for ERR051700 erratum
ERR051700 erratum is present on all S32CC-based SoCs and relates to reset. Releasing multiple Software Resettable Domains (SRDs) from reset simultaneously, may cause a false error in the fault control unit.
The workaround is to clear the SRD resets sequentially instead of simultaneously.
Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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