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Searched refs:latency (Results 1 – 23 of 23) sorted by relevance

/rk3399_ARM-atf/fdts/
H A Dfvp-base-psci-common.dtsi53 entry-latency-us = <40>;
54 exit-latency-us = <100>;
62 entry-latency-us = <500>;
63 exit-latency-us = <1000>;
H A Dmorello-fvp.dts39 entry-latency-us = <500>;
40 exit-latency-us = <1000>;
48 entry-latency-us = <150>;
49 exit-latency-us = <300>;
H A Da5ds.dts63 arm,data-latency = <1 1 1>;
64 arm,tag-latency = <1 1 1>;
H A Dmorello-soc.dts40 entry-latency-us = <500>;
41 exit-latency-us = <1000>;
49 entry-latency-us = <150>;
50 exit-latency-us = <300>;
H A Dtc-base.dtsi113 entry-latency-us = <300>;
114 exit-latency-us = <1200>;
121 entry-latency-us = <400>;
122 exit-latency-us = <1200>;
/rk3399_ARM-atf/plat/rockchip/common/scmi/
H A Dscmi_rstd.h25 uint32_t latency; member
/rk3399_ARM-atf/drivers/scmi-msg/
H A Dreset_domain.h65 uint32_t latency; member
H A Dreset_domain.c129 return_values.latency = SCMI_RESET_DOMAIN_ATTR_UNK_LAT; in reset_domain_attributes()
/rk3399_ARM-atf/docs/design_documents/
H A Dpsci_osi_mode.rst427 entry-latency-us = <130>;
428 exit-latency-us = <620>;
438 entry-latency-us = <230>;
439 exit-latency-us = <720>;
560 entry-latency-us = <549>;
561 exit-latency-us = <901>;
570 entry-latency-us = <702>;
571 exit-latency-us = <915>;
580 entry-latency-us = <523>;
581 exit-latency-us = <1244>;
[all …]
/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-juno.rst248 .. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.14)
266 .. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.13)
295 ``PSCI_ENTRY`` corresponds to the powerdown latency, ``PSCI_EXIT`` the wakeup latency, and
296 ``CFLUSH_OVERHEAD`` the latency of the cache flush operation.
476 approximates the round trip latency for handling a fast SMC at EL3 in TF.
H A Dpsci-performance-n1sdp.rst175 .. table:: ``CPU_VERSION`` latency (ns) in parallel on all cores (v2.14)
189 .. table:: ``CPU_VERSION`` latency (ns) in parallel on all cores (v2.13)
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dzynqmp_pm_api_sys.h75 uint32_t latency,
80 uint32_t latency,
H A Dzynqmp_pm_api_sys.c265 uint32_t latency, in pm_self_suspend() argument
287 latency, state, address, (address >> 32)); in pm_self_suspend()
306 uint32_t latency, uint32_t state, in pm_req_suspend() argument
313 PM_PACK_PAYLOAD5(payload, flag, PM_REQ_SUSPEND, target, ack, latency, state); in pm_req_suspend()
/rk3399_ARM-atf/plat/xilinx/common/pm_service/
H A Dpm_api_sys.c148 uint32_t latency, in pm_self_suspend() argument
170 nid, latency, state, address, (address >> 32)); in pm_self_suspend()
/rk3399_ARM-atf/docs/components/
H A Dnuma-per-cpu.rst14 memory, and CPUs within a node can access this memory with lower latency than
37 access across nodes incurs additional latency because of interconnect
39 nodes must access that data via the interconnect, leading to increased latency
46 platforms place them in the nodes with the lowest access latency.
/rk3399_ARM-atf/plat/xilinx/common/include/
H A Dpm_api_sys.h29 uint32_t latency,
/rk3399_ARM-atf/docs/plat/
H A Dnvidia-tegra.rst53 Denver also features new low latency power-state transitions, in addition
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-6.rst74 On Juno R1 we measured the round trip latency for both the ``PSCI_VERSION`` and
/rk3399_ARM-atf/include/plat/marvell/odyssey/csr/
H A Dody-csrs-pem.h1292 uint64_t latency : 64; member
2104 uint64_t latency : 64; member
/rk3399_ARM-atf/docs/
H A Dporting-guide.rst2491 Depending on the expected latency for IDE-KM interface, the platform should choose blocking
2531 Depending on the expected latency for IDE-KM interface, the platform should choose blocking
2569 Depending on the expected latency for IDE-KM interface, the platform should choose blocking
2606 Depending on the expected latency for IDE-KM interface, the platform should choose blocking
H A Dchange-log.md3865 …- change CAM setting to improve bus latency of R-Car Gen3 ([e366f8c](https://review.trustedfirmwar…
6328 …- set L2 cache data ram latency on A72 cores to 4 cycles ([aee2f33](https://review.trustedfirmware…
11168 definitions, Allow USE_COHERENT_MEM for K3, Set L2 latency on A72 cores
/rk3399_ARM-atf/docs/design/
H A Dfirmware-design.rst1525 the work and latency involved, the newer cores will "give up" mid way through if
2412 minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
/rk3399_ARM-atf/docs/getting_started/
H A Dbuild-options.rst989 reduce entry latency into EL3 even when RAS error handling is not performed