| /rk3399_ARM-atf/bl31/ |
| H A D | bl31_traps.c | 80 u_register_t elr_el3 = 0; in get_elr_el3() local
89 elr_el3 = vbar + CURRENT_EL_SPX; in get_elr_el3()
91 elr_el3 = vbar + CURRENT_EL_SP0; in get_elr_el3()
95 elr_el3 = vbar + LOWER_EL_AARCH64; in get_elr_el3()
98 return elr_el3; in get_elr_el3()
240 u_register_t elr_el3 = 0U; in inject_undef64() local
252 elr_el3 = read_ctx_reg(state, CTX_ELR_EL3); in inject_undef64()
255 write_elr_el2(elr_el3); in inject_undef64()
256 elr_el3 = get_elr_el3(old_spsr, read_vbar_el2(), to_el); in inject_undef64()
260 write_elr_el1(elr_el3); in inject_undef64()
[all …]
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| /rk3399_ARM-atf/plat/arm/board/fvp/aarch64/ |
| H A D | fvp_ea.c | 30 u_register_t elr_el3; in plat_ea_handler() local
43 elr_el3 = read_ctx_reg(el3_ctx, CTX_ELR_EL3); in plat_ea_handler()
44 elr_el3 += 4; in plat_ea_handler()
45 write_ctx_reg(el3_ctx, CTX_ELR_EL3, elr_el3); in plat_ea_handler()
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| /rk3399_ARM-atf/bl32/tsp/ |
| H A D | tsp_interrupt.c | 30 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) in tsp_update_sync_sel1_intr_stats() argument
39 read_mpidr(), elr_el3); in tsp_update_sync_sel1_intr_stats()
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| H A D | tsp_private.h | 93 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
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| /rk3399_ARM-atf/plat/nvidia/tegra/common/ |
| H A D | tegra_fiq_glue.c | 66 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); in tegra_fiq_interrupt_handler()
139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
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| /rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/ |
| H A D | tegra_gic.h | 17 uint64_t elr_el3; member
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| /rk3399_ARM-atf/bl31/aarch64/ |
| H A D | ea_delegate.S | 109 mrs x30, elr_el3
131 msr elr_el3, x30
250 mrs x3, elr_el3
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| H A D | runtime_exceptions.S | 368 mrs x17, elr_el3
537 mrs x1, elr_el3
663 mrs x28, elr_el3
702 msr elr_el3, x28
729 mrs x4, elr_el3
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| H A D | crash_reporting.S | 444 mrs x15, elr_el3
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| /rk3399_ARM-atf/services/std_svc/sdei/ |
| H A D | sdei_intr_mgmt.c | 42 uint64_t elr_el3; member
188 disp_ctx->elr_el3 = read_ctx_reg(tgt_el3, CTX_ELR_EL3); in save_event_ctx()
208 write_ctx_reg(tgt_el3, CTX_ELR_EL3, disp_ctx->elr_el3); in restore_event_ctx()
290 SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3); in setup_ns_dispatch()
696 write_elr_el2(disp_ctx->elr_el3); in sdei_event_complete()
700 write_elr_el1(disp_ctx->elr_el3); in sdei_event_complete()
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| /rk3399_ARM-atf/bl2/aarch64/ |
| H A D | bl2_run_next_image.S | 28 msr elr_el3, x0
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| /rk3399_ARM-atf/bl1/aarch64/ |
| H A D | bl1_entrypoint.S | 78 msr elr_el3, x0
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| H A D | bl1_exceptions.S | 182 msr elr_el3, x0
260 mrs x17, elr_el3
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| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | wa_cve_2017_5715_bpiall.S | 58 mrs x7, elr_el3
85 msr elr_el3, x11
277 msr elr_el3, x7
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| H A D | neoverse_n1.S | 269 mrs x3, elr_el3
271 msr elr_el3, x3
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| /rk3399_ARM-atf/plat/qti/qtiseclib/inc/ |
| H A D | qtiseclib_defs.h | 77 uint64_t elr_el3; member
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| /rk3399_ARM-atf/plat/nxp/common/sip_svc/aarch64/ |
| H A D | sipsvc.S | 56 msr elr_el3, x1
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| /rk3399_ARM-atf/plat/hisilicon/hikey/aarch64/ |
| H A D | hikey_helpers.S | 117 mrs x4, elr_el3
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/aarch64/ |
| H A D | hikey960_helpers.S | 121 mrs x4, elr_el3
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| /rk3399_ARM-atf/plat/st/stm32mp2/aarch64/ |
| H A D | stm32mp2_helper.S | 203 mrs x4, elr_el3
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| /rk3399_ARM-atf/plat/qti/qtiseclib/src/ |
| H A D | qtiseclib_cb_interface.c | 142 qti_ns_ctx->elr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_ELR_EL3); in qtiseclib_cb_get_ns_ctx()
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| /rk3399_ARM-atf/plat/renesas/common/aarch64/ |
| H A D | plat_helpers.S | 198 msr elr_el3, x0
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| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context.S | 638 msr elr_el3, x17
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch_helpers.h | 357 DEFINE_SYSREG_RW_FUNCS(elr_el3) in DECLARE_SYSREG128_RW_FUNCS()
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| /rk3399_ARM-atf/docs/design/ |
| H A D | interrupt-framework-design.rst | 788 now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
|