180c50eeaSVarun Wadekar /* 280c50eeaSVarun Wadekar * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 367db3231SVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 480c50eeaSVarun Wadekar * 580c50eeaSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 680c50eeaSVarun Wadekar */ 780c50eeaSVarun Wadekar 867db3231SVarun Wadekar #ifndef TEGRA_GIC_H 967db3231SVarun Wadekar #define TEGRA_GIC_H 1080c50eeaSVarun Wadekar 1109d40e0eSAntonio Nino Diaz #include <common/interrupt_props.h> 1280c50eeaSVarun Wadekar 1380c50eeaSVarun Wadekar /******************************************************************************* 1480c50eeaSVarun Wadekar * Per-CPU struct describing FIQ state to be stored 1580c50eeaSVarun Wadekar ******************************************************************************/ 1680c50eeaSVarun Wadekar typedef struct pcpu_fiq_state { 1780c50eeaSVarun Wadekar uint64_t elr_el3; 1880c50eeaSVarun Wadekar uint64_t spsr_el3; 1980c50eeaSVarun Wadekar } pcpu_fiq_state_t; 2080c50eeaSVarun Wadekar 2180c50eeaSVarun Wadekar /******************************************************************************* 22*1b491eeaSElyes Haouas * Function declarations 2380c50eeaSVarun Wadekar ******************************************************************************/ 2480c50eeaSVarun Wadekar void tegra_gic_cpuif_deactivate(void); 2580c50eeaSVarun Wadekar void tegra_gic_init(void); 2680c50eeaSVarun Wadekar void tegra_gic_pcpu_init(void); 2780c50eeaSVarun Wadekar void tegra_gic_setup(const interrupt_prop_t *interrupt_props, 2880c50eeaSVarun Wadekar unsigned int interrupt_props_num); 2980c50eeaSVarun Wadekar 3067db3231SVarun Wadekar #endif /* TEGRA_GIC_H */ 31