1*6c09af9fSZelalem Aweke/* 2*6c09af9fSZelalem Aweke * Copyright (c) 2021, Arm Limited. All rights reserved. 3*6c09af9fSZelalem Aweke * 4*6c09af9fSZelalem Aweke * SPDX-License-Identifier: BSD-3-Clause 5*6c09af9fSZelalem Aweke */ 6*6c09af9fSZelalem Aweke 7*6c09af9fSZelalem Aweke#include <arch.h> 8*6c09af9fSZelalem Aweke#include <asm_macros.S> 9*6c09af9fSZelalem Aweke#include <common/bl_common.h> 10*6c09af9fSZelalem Aweke 11*6c09af9fSZelalem Aweke .globl bl2_run_next_image 12*6c09af9fSZelalem Aweke 13*6c09af9fSZelalem Aweke 14*6c09af9fSZelalem Awekefunc bl2_run_next_image 15*6c09af9fSZelalem Aweke mov x20,x0 16*6c09af9fSZelalem Aweke /* --------------------------------------------- 17*6c09af9fSZelalem Aweke * MMU needs to be disabled because both BL2 and BL31 execute 18*6c09af9fSZelalem Aweke * in EL3, and therefore share the same address space. 19*6c09af9fSZelalem Aweke * BL31 will initialize the address space according to its 20*6c09af9fSZelalem Aweke * own requirement. 21*6c09af9fSZelalem Aweke * --------------------------------------------- 22*6c09af9fSZelalem Aweke */ 23*6c09af9fSZelalem Aweke bl disable_mmu_icache_el3 24*6c09af9fSZelalem Aweke tlbi alle3 25*6c09af9fSZelalem Aweke bl bl2_el3_plat_prepare_exit 26*6c09af9fSZelalem Aweke 27*6c09af9fSZelalem Aweke ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 28*6c09af9fSZelalem Aweke msr elr_el3, x0 29*6c09af9fSZelalem Aweke msr spsr_el3, x1 30*6c09af9fSZelalem Aweke 31*6c09af9fSZelalem Aweke ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 32*6c09af9fSZelalem Aweke ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 33*6c09af9fSZelalem Aweke ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 34*6c09af9fSZelalem Aweke ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 35*6c09af9fSZelalem Aweke exception_return 36*6c09af9fSZelalem Awekeendfunc bl2_run_next_image 37