14f6ad66aSAchin Gupta/* 2*6c09af9fSZelalem Aweke * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 54f6ad66aSAchin Gupta */ 64f6ad66aSAchin Gupta 7c10bd2ceSSandrine Bailleux#include <arch.h> 8*6c09af9fSZelalem Aweke#include <common/bl_common.h> 952010cc7SSandrine Bailleux#include <el3_common_macros.S> 104f6ad66aSAchin Gupta 119f98aa1aSJeenu Viswambharan .globl bl1_entrypoint 12*6c09af9fSZelalem Aweke .globl bl1_run_bl2_in_root 134f6ad66aSAchin Gupta 144f6ad66aSAchin Gupta 154f6ad66aSAchin Gupta /* ----------------------------------------------------- 169f98aa1aSJeenu Viswambharan * bl1_entrypoint() is the entry point into the trusted 174f6ad66aSAchin Gupta * firmware code when a cpu is released from warm or 184f6ad66aSAchin Gupta * cold reset. 194f6ad66aSAchin Gupta * ----------------------------------------------------- 204f6ad66aSAchin Gupta */ 214f6ad66aSAchin Gupta 220a30cf54SAndrew Thoelkefunc bl1_entrypoint 23bf031bbaSSandrine Bailleux /* --------------------------------------------------------------------- 24bf031bbaSSandrine Bailleux * If the reset address is programmable then bl1_entrypoint() is 25bf031bbaSSandrine Bailleux * executed only on the cold boot path. Therefore, we can skip the warm 26bf031bbaSSandrine Bailleux * boot mailbox mechanism. 27bf031bbaSSandrine Bailleux * --------------------------------------------------------------------- 28bf031bbaSSandrine Bailleux */ 2952010cc7SSandrine Bailleux el3_entrypoint_common \ 3018f2efd6SDavid Cunado _init_sctlr=1 \ 31bf031bbaSSandrine Bailleux _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 32a9bec67dSSandrine Bailleux _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 3352010cc7SSandrine Bailleux _init_memory=1 \ 3452010cc7SSandrine Bailleux _init_c_runtime=1 \ 35da90359bSManish Pandey _exception_vectors=bl1_exceptions \ 36da90359bSManish Pandey _pie_fixup_size=0 374f6ad66aSAchin Gupta 38cd7d6b0eSAntonio Nino Diaz /* -------------------------------------------------------------------- 39dbad1bacSVikram Kanigiri * Initialize platform and jump to our c-entry point 407baff11fSYatharth Kochar * for this type of reset. 41cd7d6b0eSAntonio Nino Diaz * -------------------------------------------------------------------- 42dbad1bacSVikram Kanigiri */ 43dbad1bacSVikram Kanigiri bl bl1_main 447baff11fSYatharth Kochar 457baff11fSYatharth Kochar /* -------------------------------------------------- 467baff11fSYatharth Kochar * Do the transition to next boot image. 477baff11fSYatharth Kochar * -------------------------------------------------- 487baff11fSYatharth Kochar */ 49*6c09af9fSZelalem Aweke#if ENABLE_RME 50*6c09af9fSZelalem Aweke b bl1_run_bl2_in_root 51*6c09af9fSZelalem Aweke#else 527baff11fSYatharth Kochar b el3_exit 53*6c09af9fSZelalem Aweke#endif 548b779620SKévin Petitendfunc bl1_entrypoint 55*6c09af9fSZelalem Aweke 56*6c09af9fSZelalem Aweke /* ----------------------------------------------------- 57*6c09af9fSZelalem Aweke * void bl1_run_bl2_in_root(); 58*6c09af9fSZelalem Aweke * This function runs BL2 in root/EL3 when RME is enabled. 59*6c09af9fSZelalem Aweke * ----------------------------------------------------- 60*6c09af9fSZelalem Aweke */ 61*6c09af9fSZelalem Aweke 62*6c09af9fSZelalem Awekefunc bl1_run_bl2_in_root 63*6c09af9fSZelalem Aweke /* read bl2_ep_info */ 64*6c09af9fSZelalem Aweke adrp x20, bl2_ep_info 65*6c09af9fSZelalem Aweke add x20, x20, :lo12:bl2_ep_info 66*6c09af9fSZelalem Aweke ldr x20, [x20] 67*6c09af9fSZelalem Aweke 68*6c09af9fSZelalem Aweke /* --------------------------------------------- 69*6c09af9fSZelalem Aweke * MMU needs to be disabled because BL2 executes 70*6c09af9fSZelalem Aweke * in EL3. It will initialize the address space 71*6c09af9fSZelalem Aweke * according to its own requirements. 72*6c09af9fSZelalem Aweke * --------------------------------------------- 73*6c09af9fSZelalem Aweke */ 74*6c09af9fSZelalem Aweke bl disable_mmu_icache_el3 75*6c09af9fSZelalem Aweke tlbi alle3 76*6c09af9fSZelalem Aweke 77*6c09af9fSZelalem Aweke ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 78*6c09af9fSZelalem Aweke msr elr_el3, x0 79*6c09af9fSZelalem Aweke msr spsr_el3, x1 80*6c09af9fSZelalem Aweke 81*6c09af9fSZelalem Aweke ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 82*6c09af9fSZelalem Aweke ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 83*6c09af9fSZelalem Aweke ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 84*6c09af9fSZelalem Aweke ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 85*6c09af9fSZelalem Aweke exception_return 86*6c09af9fSZelalem Awekeendfunc bl1_run_bl2_in_root 87