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/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.c32 #define CLKDIV_5BITS_SHF0(div) BITS_WITH_WMASK(div, 0x1f, 0) argument
33 #define CLKDIV_5BITS_SHF8(div) BITS_WITH_WMASK(div, 0x1f, 8) argument
35 #define CLKDIV_4BITS_SHF0(div) BITS_WITH_WMASK(div, 0xf, 0) argument
36 #define CLKDIV_2BITS_SHF4(div) BITS_WITH_WMASK(div, 0x3, 4) argument
281 struct pvtpll_table *div; in rk3568_apll_set_rate() local
284 div = rkclk_get_pll_config(rate); in rk3568_apll_set_rate()
285 if (div == NULL) in rk3568_apll_set_rate()
288 if (PVTPLL_NEED(type, div->length)) { in rk3568_apll_set_rate()
294 0xffff0000 | div->length); in rk3568_apll_set_rate()
310 (div->fbdiv << RK3568_PLLCON0_FBDIV_SHIFT)); in rk3568_apll_set_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/common/scmi/
H A Drockchip_common_clock.c59 unsigned long parent_rate, sel, div; in clk_scmi_common_get_rate() local
64 div = mmio_read_32(clock->info[DIV_ADDR_INFO]) >> in clk_scmi_common_get_rate()
66 div = div & (BIT(clock->info[DIV_WIDTH_INFO]) - 1); in clk_scmi_common_get_rate()
69 return parent_rate / (div + 1); in clk_scmi_common_get_rate()
75 int i = 0, sel_mask, div_mask, best_sel = 0, best_div = 0, div; in clk_scmi_common_set_rate() local
85 div = DIV_ROUND_UP(parent_rate, rate); in clk_scmi_common_set_rate()
86 if (div > div_mask + 1) in clk_scmi_common_set_rate()
87 div = div_mask + 1; in clk_scmi_common_set_rate()
89 BITS_WITH_WMASK(div - 1, div_mask, in clk_scmi_common_set_rate()
108 div = DIV_ROUND_UP(parent_rate, rate); in clk_scmi_common_set_rate()
[all …]
/rk3399_ARM-atf/drivers/delay_timer/
H A Dgeneric_delay_timer.c51 void generic_delay_timer_init_args(uint32_t mult, uint32_t div) in generic_delay_timer_init_args() argument
55 ops.clk_div = div; in generic_delay_timer_init_args()
62 mult, div); in generic_delay_timer_init_args()
73 unsigned int div = plat_get_syscnt_freq2(); in generic_delay_timer_init() local
76 while (((mult % 10U) == 0U) && ((div % 10U) == 0U)) { in generic_delay_timer_init()
78 div /= 10U; in generic_delay_timer_init()
81 generic_delay_timer_init_args(mult, div); in generic_delay_timer_init()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c60 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) argument
61 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) argument
62 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift) argument
63 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift) argument
64 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift) argument
65 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift) argument
305 int div; in clk_cpul_set_rate() local
346 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpul_set_rate()
348 CLKDIV_5BITS_SHF(div, 0) | CLKDIV_5BITS_SHF(div, 7)); in clk_cpul_set_rate()
350 CLKDIV_5BITS_SHF(div, 0) | CLKDIV_5BITS_SHF(div, 7)); in clk_cpul_set_rate()
[all …]
/rk3399_ARM-atf/drivers/nxp/timer/
H A Dnxp_timer.c60 static void delay_timer_init_args(uint32_t mult, uint32_t div) in delay_timer_init_args() argument
64 ops.clk_div = div; in delay_timer_init_args()
69 mult, div); in delay_timer_init_args()
81 unsigned int div; in delay_timer_init() local
98 div = counter_base_frequency; in delay_timer_init()
101 while ((mult % 10U == 0U) && (div % 10U == 0U)) { in delay_timer_init()
103 div /= 10U; in delay_timer_init()
110 delay_timer_init_args(mult, div); in delay_timer_init()
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c60 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) argument
61 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) argument
62 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift) argument
63 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift) argument
64 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift) argument
65 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift) argument
403 int div; in clk_cpul_set_rate() local
458 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpul_set_rate()
460 CLKDIV_5BITS_SHF(div, 7)); in clk_cpul_set_rate()
530 int src, div; in clk_scmi_cpul_get_rate() local
[all …]
/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/
H A Dboot_init_dram_config.c1770 void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) in boardcnf_get_brd_clk() argument
1776 *div = 3; in boardcnf_get_brd_clk()
1782 *div = 3; in boardcnf_get_brd_clk()
1786 *div = 3; in boardcnf_get_brd_clk()
1790 *div = 3; in boardcnf_get_brd_clk()
1794 *div = 3; in boardcnf_get_brd_clk()
1801 void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) in boardcnf_get_ddr_mbps() argument
1815 *div = 1; in boardcnf_get_ddr_mbps()
1819 *div = 1; in boardcnf_get_ddr_mbps()
1823 *div = 1; in boardcnf_get_ddr_mbps()
[all …]
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_console_setup.c52 uint32_t div; in uniphier_console_get_base() local
59 div = mmio_read_32(base + UNIPHIER_UART_DLR); in uniphier_console_get_base()
60 if (div) in uniphier_console_get_base()
/rk3399_ARM-atf/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h47 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
50 ((div) << CLK_DIV_SHIFT) |\
69 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
71 (div)))
H A Dstm32mp25-clksrc.h47 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
50 ((div) << CLK_DIV_SHIFT) |\
69 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
71 (div)))
H A Dstm32mp13-clksrc.h68 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
70 (div)))
H A Dstm32mp15-clksrc.h42 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
44 (div))
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.c118 .div = NA_DIV, \
131 .div = NA_DIV, \
144 .div = NA_DIV, \
158 .div = NA_DIV, \
172 .div = NA_DIV, \
185 .div = NA_DIV, \
198 .div = NA_DIV, \
219 uint8_t div:4; member
260 .div = NA_DIV,
272 .div = NA_DIV,
[all …]
H A Dpm_api_clock.h305 uint32_t *div);
/rk3399_ARM-atf/include/arch/aarch32/
H A Dasm_macros.S217 .macro softudiv div:req,top:req,bot:req,temp:req
225 mov \div, #0
230 ADC \div, \div, \div
/rk3399_ARM-atf/drivers/rpi3/sdhost/
H A Drpi3_sdhost.c396 uint32_t div; in rpi3_sdhost_set_clock() local
404 div = max_clk / clk; in rpi3_sdhost_set_clock()
405 if (div < 2) in rpi3_sdhost_set_clock()
406 div = 2; in rpi3_sdhost_set_clock()
408 if ((max_clk / div) > clk) in rpi3_sdhost_set_clock()
409 div++; in rpi3_sdhost_set_clock()
411 div -= 2; in rpi3_sdhost_set_clock()
412 if (div > HC_CLOCKDIVISOR_MAXVAL) in rpi3_sdhost_set_clock()
413 div = HC_CLOCKDIVISOR_MAXVAL; in rpi3_sdhost_set_clock()
415 rpi3_sdhost_params.clk_rate = max_clk / (div + 2); in rpi3_sdhost_set_clock()
[all …]
/rk3399_ARM-atf/plat/aspeed/ast2700/
H A Dplat_bl31_setup.c143 uint32_t mul = 1, div = 1; in plat_get_pll_rate() local
181 div = (pll_reg.b.p + 1); in plat_get_pll_rate()
185 div = (pll_reg.b.p + 1); in plat_get_pll_rate()
189 rate = ((CLKIN_25M * mul) / div); in plat_get_pll_rate()
/rk3399_ARM-atf/drivers/synopsys/emmc/
H A Ddw_mmc.c160 int div; in dw_set_clk() local
164 for (div = 1; div < 256; div++) { in dw_set_clk()
165 if ((dw_params.clk_rate / (2 * div)) <= clk) { in dw_set_clk()
169 assert(div < 256); in dw_set_clk()
180 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div); in dw_set_clk()
/rk3399_ARM-atf/include/lib/
H A Dutils_def.h104 #define div_round_up(val, div) __extension__ ({ \ argument
105 __typeof__(div) _div = (div); \
106 ((val) + _div - (__typeof__(div)) 1) / _div; \
/rk3399_ARM-atf/include/drivers/
H A Dgeneric_delay_timer.h12 void generic_delay_timer_init_args(uint32_t mult, uint32_t div);
/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.c115 unsigned int pre_div = 1U, div = 1U; in imx_usdhc_set_clk() local
124 while (((sdhc_clk / (div * pre_div)) > clk) && (div < 16U)) { in imx_usdhc_set_clk()
125 div++; in imx_usdhc_set_clk()
129 div -= 1; in imx_usdhc_set_clk()
130 clk = (pre_div << 8) | (div << 4); in imx_usdhc_set_clk()
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.c243 for (clkt = table; clkt->div; clkt++) { in _get_table_div()
245 return clkt->div; in _get_table_div()
730 const struct div_cfg *divider = &priv->div[div_id]; in clk_stm32_div_get_value()
743 const struct div_cfg *divider = &priv->div[div_id]; in _clk_stm32_divider_recalc()
745 unsigned int div = 0U; in _clk_stm32_divider_recalc() local
747 div = _get_div(divider->table, val, divider->flags, divider->width); in _clk_stm32_divider_recalc()
748 if (div == 0U) { in _clk_stm32_divider_recalc()
752 return div_round_up((uint64_t)prate, div); in _clk_stm32_divider_recalc()
779 divider = &priv->div[div_id]; in clk_stm32_set_div()
900 if (cfg->div == 0U) { in fixed_factor_recalc_rate()
[all …]
H A Dclk-stm32-core.h25 uint16_t div; member
72 const struct div_cfg *div; member
252 uint8_t div; member
264 .div = (_div),\
/rk3399_ARM-atf/plat/intel/soc/common/drivers/qspi/
H A Dcadence_qspi.c32 int cad_qspi_set_baudrate_div(uint32_t div) in cad_qspi_set_baudrate_div() argument
34 if (div > 0xf) in cad_qspi_set_baudrate_div()
39 CAD_QSPI_CFG_BAUDDIV(div)); in cad_qspi_set_baudrate_div()
/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Ddram.c570 static void set_cgc2_ddrclk(uint8_t src, uint8_t div) in set_cgc2_ddrclk() argument
577 mmio_write_32(IMX_CGC2_BASE + 0x40, (src << 28) | (div << 21)); in set_cgc2_ddrclk()

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