32 #define CLKDIV_5BITS_SHF0(div)	BITS_WITH_WMASK(div, 0x1f, 0)  argument
33 #define CLKDIV_5BITS_SHF8(div)	BITS_WITH_WMASK(div, 0x1f, 8)  argument
35 #define CLKDIV_4BITS_SHF0(div)	BITS_WITH_WMASK(div, 0xf, 0)  argument
36 #define CLKDIV_2BITS_SHF4(div)	BITS_WITH_WMASK(div, 0x3, 4)  argument
281 	struct pvtpll_table *div;  in rk3568_apll_set_rate()  local
284 	div = rkclk_get_pll_config(rate);  in rk3568_apll_set_rate()
285 	if (div == NULL)  in rk3568_apll_set_rate()
288 	if (PVTPLL_NEED(type, div->length)) {  in rk3568_apll_set_rate()
294 			      0xffff0000 | div->length);  in rk3568_apll_set_rate()
310 		      (div->fbdiv << RK3568_PLLCON0_FBDIV_SHIFT));  in rk3568_apll_set_rate()
314 		      (div->postdiv1 << RK3568_PLLCON0_POSTDIV1_SHIFT));  in rk3568_apll_set_rate()
318 		      (div->refdiv << RK3568_PLLCON1_REFDIV_SHIFT));  in rk3568_apll_set_rate()
322 		      (div->postdiv2 << RK3568_PLLCON1_POSTDIV2_SHIFT));  in rk3568_apll_set_rate()
326 		      (div->dsmpd << RK3568_PLLCON1_DSMPD_SHIFT));  in rk3568_apll_set_rate()
382 	int div = 0, ret = 0;  in clk_cpu_set_rate()  local
415 	div = DIV_ROUND_UP(rate, 300000000);  in clk_cpu_set_rate()
416 	div = div - 1;  in clk_cpu_set_rate()
419 		      CLKDIV_5BITS_SHF8(div) | CLKDIV_5BITS_SHF0(div));  in clk_cpu_set_rate()
421 	div = DIV_ROUND_UP(rate, 300000000);  in clk_cpu_set_rate()
422 	div = div - 1;  in clk_cpu_set_rate()
424 		CLKDIV_5BITS_SHF8(div) | CLKDIV_5BITS_SHF0(div));  in clk_cpu_set_rate()
474 	int div;  in clk_scmi_gpu_get_rate()  local
479 		div = mmio_read_32(CRU_BASE + RK3568_CLK_SEL(6));  in clk_scmi_gpu_get_rate()
480 		div = div & 0x000f;  in clk_scmi_gpu_get_rate()
481 		return GPLL_RATE / (div + 1);  in clk_scmi_gpu_get_rate()
488 	int div;  in clk_gpu_set_rate()  local
514 	div = DIV_ROUND_UP(GPLL_RATE, rate);  in clk_gpu_set_rate()
516 	mmio_write_32(CRU_BASE + RK3568_CLK_SEL(6), CLKDIV_4BITS_SHF0((div - 1)));  in clk_gpu_set_rate()
539 	int div;  in clk_scmi_npu_get_rate()  local
544 		div = mmio_read_32(CRU_BASE + RK3568_CLK_SEL(7));  in clk_scmi_npu_get_rate()
545 		div = div & 0x000f;  in clk_scmi_npu_get_rate()
546 		return GPLL_RATE / (div + 1);  in clk_scmi_npu_get_rate()
553 	int div;  in clk_npu_set_rate()  local
580 		div = DIV_ROUND_UP(GPLL_RATE, rate);  in clk_npu_set_rate()
583 			      CLKDIV_4BITS_SHF0((div - 1)));  in clk_npu_set_rate()