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Searched refs:core_id (Results 1 – 14 of 14) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx8m/include/
H A Dgpc.h20 #define A53_CORE_WUP_SRC(core_id) (1 << ((core_id) < 2 ? 28 + (core_id) : 22 + (core_id) - 2)) argument
21 #define COREx_PGC_PCR(core_id) (0x800 + (core_id) * 0x40) argument
22 #define COREx_WFI_PDN(core_id) (1 << ((core_id) < 2 ? (core_id) * 2 : ((core_id) - 2) * 2 + 16)) argument
23 #define COREx_IRQ_WUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 8)) : (1 << ((core_id) * 2 … argument
24 #define COREx_LPM_PUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 9)) : (1 << ((core_id) * 2 … argument
26 #define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2)) argument
27 #define SLT_COREx_PUP_ACK(core_id) ((core_id) < 2 ? (1 << ((core_id) + 16)) : (1 << ((core_id) + 27… argument
82 void imx_gpc_set_a53_core_awake(uint32_t core_id);
/rk3399_ARM-atf/plat/imx/imx93/
H A Dimx93_psci.c62 void imx_set_cpu_boot_entry(unsigned int core_id, uint64_t boot_entry) in imx_set_cpu_boot_entry() argument
65 mmio_write_32(BLK_CTRL_S_BASE + CA55_RVBADDR0_L + core_id * 8, boot_entry >> 2); in imx_set_cpu_boot_entry()
70 unsigned int core_id; in imx_pwr_domain_on() local
72 core_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_pwr_domain_on()
74 imx_set_cpu_boot_entry(core_id, secure_entrypoint); in imx_pwr_domain_on()
83 mmio_clrbits_32(SRC_SLICE(SRC_A55C0 + core_id) + 0x24, BIT(2) | BIT(0)); in imx_pwr_domain_on()
85 mmio_setbits_32(SRC_SLICE(SRC_A55C0 + core_id) + 0x24, BIT(2) | BIT(0)); in imx_pwr_domain_on()
87 mmio_clrbits_32(BLK_CTRL_S_BASE + CA55_CPUWAIT, BIT(core_id)); in imx_pwr_domain_on()
90 gpc_assert_sw_wakeup(CPU_A55C0 + core_id); in imx_pwr_domain_on()
99 unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_pwr_domain_on_finish() local
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/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_psci_common.c69 void imx_set_cpu_boot_entry(uint32_t core_id, uint64_t boot_entry, in imx_set_cpu_boot_entry() argument
74 SCMI_CPU_A55_ID(core_id), in imx_set_cpu_boot_entry()
80 uint32_t core_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_pwr_domain_on() local
83 imx_set_cpu_boot_entry(core_id, in imx_pwr_domain_on()
87 scmi_core_start(imx9_scmi_handle, SCMI_CPU_A55_ID(core_id)); in imx_pwr_domain_on()
92 scmi_core_nonIrq_wake_set(imx9_scmi_handle, SCMI_CPU_A55_ID(core_id), 0U, 1U, mask); in imx_pwr_domain_on()
96 SCMI_CPU_A55_PD(core_id), in imx_pwr_domain_on()
102 SCMI_CPU_A55_ID(core_id), in imx_pwr_domain_on()
111 uint32_t core_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_pwr_domain_on_finish() local
114 SCMI_CPU_A55_ID(core_id), in imx_pwr_domain_on_finish()
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H A Dimx9_sys_sleep.c198 void imx9_sys_sleep_prepare(uint32_t core_id) in imx9_sys_sleep_prepare() argument
216 imx_set_sys_wakeup(core_id, true); in imx9_sys_sleep_prepare()
221 void imx9_sys_sleep_unprepare(uint32_t core_id) in imx9_sys_sleep_unprepare() argument
239 imx_set_sys_wakeup(core_id, false); in imx9_sys_sleep_unprepare()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dgpc.c46 static void gpc_imr_core_spin_lock(unsigned int core_id) in gpc_imr_core_spin_lock() argument
48 spin_lock(&gpc_imr_lock[core_id]); in gpc_imr_core_spin_lock()
51 static void gpc_imr_core_spin_unlock(unsigned int core_id) in gpc_imr_core_spin_unlock() argument
53 spin_unlock(&gpc_imr_lock[core_id]); in gpc_imr_core_spin_unlock()
56 static void gpc_save_imr_lpm(unsigned int core_id, unsigned int imr_idx) in gpc_save_imr_lpm() argument
58 uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4; in gpc_save_imr_lpm()
60 gpc_imr_core_spin_lock(core_id); in gpc_save_imr_lpm()
62 gpc_saved_imrs[core_id + imr_idx * 4] = mmio_read_32(reg); in gpc_save_imr_lpm()
65 gpc_imr_core_spin_unlock(core_id); in gpc_save_imr_lpm()
68 static void gpc_restore_imr_lpm(unsigned int core_id, unsigned int imr_idx) in gpc_restore_imr_lpm() argument
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H A Dimx8mq_psci.c47 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_off() local
50 imx_set_cpu_pwr_off(core_id); in imx_pwr_domain_off()
63 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend() local
68 imx_set_cpu_secure_entry(core_id, base_addr); in imx_domain_suspend()
69 imx_set_cpu_lpm(core_id, true); in imx_domain_suspend()
77 imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state)); in imx_domain_suspend()
82 imx_set_sys_lpm(core_id, true); in imx_domain_suspend()
91 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend_finish() local
97 imx_set_sys_lpm(core_id, false); in imx_domain_suspend_finish()
103 imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN); in imx_domain_suspend_finish()
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/rk3399_ARM-atf/plat/imx/imx8m/
H A Dgpc_common.c37 void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint) in imx_set_cpu_secure_entry() argument
44 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3), in imx_set_cpu_secure_entry()
46 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4, in imx_set_cpu_secure_entry()
50 void imx_set_cpu_pwr_off(unsigned int core_id) in imx_set_cpu_pwr_off() argument
56 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_off()
61 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
64 void imx_set_cpu_pwr_on(unsigned int core_id) in imx_set_cpu_pwr_on() argument
69 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_on()
74 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
76 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
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H A Dimx8m_psci_common.c43 unsigned int core_id; in imx_pwr_domain_on() local
46 core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_on()
48 imx_set_cpu_secure_entry(core_id, base_addr); in imx_pwr_domain_on()
49 imx_set_cpu_pwr_on(core_id); in imx_pwr_domain_on()
63 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_off() local
66 imx_set_cpu_pwr_off(core_id); in imx_pwr_domain_off()
108 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend() local
112 imx_set_cpu_secure_entry(core_id, base_addr); in imx_domain_suspend()
113 imx_set_cpu_lpm(core_id, true); in imx_domain_suspend()
121 imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state)); in imx_domain_suspend()
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/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/
H A Ds32g2_soc.c24 unsigned int cluster_id, cpu_id, core_id; in plat_core_pos_by_mpidr() local
41 core_id = s32g2_core_pos_by_mpidr(mpidr_priv); in plat_core_pos_by_mpidr()
42 if (core_id >= PLATFORM_CORE_COUNT) { in plat_core_pos_by_mpidr()
46 return (int)core_id; in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/imx/imx9/common/include/
H A Dimx9_sys_sleep.h56 void imx9_sys_sleep_prepare(uint32_t core_id);
57 void imx9_sys_sleep_unprepare(uint32_t core_id);
H A Dimx9_psci_common.h22 void imx_set_cpu_boot_entry(uint32_t core_id, uint64_t boot_entry, uint32_t flag);
/rk3399_ARM-atf/services/std_svc/spmd/
H A Dspmd_private.h81 void spmd_setup_context(unsigned int core_id);
H A Dspmd_main.c181 void spmd_setup_context(unsigned int core_id) in spmd_setup_context() argument
196 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4, core_id); in spmd_setup_context()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/include/
H A Dt194_nvg.h324 uint32_t core_id : U(4); member