Merge changes I1bfa797e,I0ec7a70e into integration

* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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Merge changes from topic "imx8m_misc_changes" into integration

* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(im

Merge changes from topic "imx8m_misc_changes" into integration

* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(imx8mq): correct the slot ack setting for STOP mode
feat(imx8mq): add anamix pll override setting for DSM mode
feat(imx8mq): add workaround code for ERR11171 on imx8mq
feat(imx8mq): add the dram retention support for imx8mq
feat(imx8mq): add version for B2
fix(imx8m): backup mr12/14 value from lpddr4 chip
fix(imx8m): add ddr4 dvfs sw workaround for ERR050712
fix(imx8m): fix coverity out of bound access issue
fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0
feat(imx8m): add more dram pll setting
fix(imx8m): fix the current fsp init
fix(imx8m): fix the rank to rank space issue
fix(imx8m): fix the dfiphymaster setting after dvfs
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
fix(imx8m): correct the rank info get fro mstr
feat(imx8m): fix the ddr4 dvfs random hang on imx8m

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feat(imx8mq): correct the slot ack setting for STOP mode

A53 core's power up ack need to be used when system resume
from DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I47fb33c058

feat(imx8mq): correct the slot ack setting for STOP mode

A53 core's power up ack need to be used when system resume
from DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I47fb33c0582ae5f483ffaa887f95e27bd47875f7

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feat(imx8mq): add anamix pll override setting for DSM mode

Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.

Signed-off-by: Jack

feat(imx8mq): add anamix pll override setting for DSM mode

Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ibe954bc7c4a7b453ace13f8e4b6a335e6d4856c3

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feat(imx8mq): add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR
registers in GPC in order to unmask the IRQ0, still generated
by the 12bit in IOMUX_G

feat(imx8mq): add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR
registers in GPC in order to unmask the IRQ0, still generated
by the 12bit in IOMUX_GPR register (which now remains always set),
so it can only wake up one core at the time.Also, this entire
workaround has now been moved here in TF-A, allowing the kernel
side to be minimal.

Another advantage this workaround brings is the removal of the
50us delay (which was necessary before in gic_raise_softirq in
kernel) by allowing the core that is waking up to mask his own
IRQ0 in the suspend finish callback.

One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from
asserting the 12th bit in IOMUX_GPR and leaving the IMR1 1st bit
on for each core to exactly the reverse, that is, leaving the
IOMUX_GPR 12th bit always set and then masking/unmasking the IMR1
1st bit for each independent core, we need to use the imx_gpc_core_wake
to wake up the cores.

Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off)
from kernel(gic_raise_softirq), since the new cpuidle workaround
does not need it in order to clean the IOMUX_GPC 12bit. For now,
the udelay seems to be still needed in order to delay the affinity
info OFF for the dying core. This is something that needs further
investigation.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9f17ff6fc3452b8225a50b232964712aafeab78a

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Merge "feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear" into integration

feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear

After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.

feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear

After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.

for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.

2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.

so add udelay 100 to safely clear the SRC bit 0.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I52e8e7739fdaaf86442bcd148e768b6af38bcdb7

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Merge "plat: imx8m: Fix the race condition during cpu hotplug" into integration

plat: imx8m: Fix the race condition during cpu hotplug

CPU hotplug & cpuidle have some race condition when doing CPU hotplug
stress test. different CPU cores have the chance to access the same
GPC r

plat: imx8m: Fix the race condition during cpu hotplug

CPU hotplug & cpuidle have some race condition when doing CPU hotplug
stress test. different CPU cores have the chance to access the same
GPC register(A53_AD), so lock is necessary to do exlusive access.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I1296592e05fa78429c3f0fac066951521db755e3

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Merge changes I286b925e,I1151c2bc into integration

* changes:
plat: imx8mq: Only keep IRQ 32 unmasked
plat: imx8mq: gpc: Enable all power domain by default

plat: imx8mq: Only keep IRQ 32 unmasked

Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible
by 32.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I286b925ee

plat: imx8mq: Only keep IRQ 32 unmasked

Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible
by 32.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I286b925eead89218cfeddd82f53a634f3447d212

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plat: imx8mq: gpc: Enable all power domain by default

This is similar to imx8mm and allows uboot to run fastboot over USB otg.

There is a different set of power domains on 8mq but same bits covers

plat: imx8mq: gpc: Enable all power domain by default

This is similar to imx8mm and allows uboot to run fastboot over USB otg.

There is a different set of power domains on 8mq but same bits covers
all off them.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I1151c2bc2d32b1e02b4db16285b3d30cabc0d64d

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Merge pull request #1859 from JackyBai/master

refact the imx8m common code and add the imx8mm support

plat: imx8m: refactor the code to make it reusable

for the i.MX8M SOCs, part of the code for gpc
and PSCI implementation can be reused and make it
common for all these SoCs. this patch extracts
the

plat: imx8m: refactor the code to make it reusable

for the i.MX8M SOCs, part of the code for gpc
and PSCI implementation can be reused and make it
common for all these SoCs. this patch extracts
the common part for reuse.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1653 from JackyBai/master

Add NXP i.MX8MQ basic support

plat: imx: Add i.MX8MQ basic support

i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consum

plat: imx: Add i.MX8MQ basic support

i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consumer home audio to industrial building
automation and mobile computers

this patchset add the basic supoort to boot up
the 4 X A53. more feature will be added later.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

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