37 void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint)  in imx_set_cpu_secure_entry()  argument
44 	mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3),  in imx_set_cpu_secure_entry()
46 	mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4,  in imx_set_cpu_secure_entry()
50 void imx_set_cpu_pwr_off(unsigned int core_id)  in imx_set_cpu_pwr_off()  argument
56 	mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id));  in imx_set_cpu_pwr_off()
61 	mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);  in imx_set_cpu_pwr_off()
64 void imx_set_cpu_pwr_on(unsigned int core_id)  in imx_set_cpu_pwr_on()  argument
69 	mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id));  in imx_set_cpu_pwr_on()
74 	mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id));  in imx_set_cpu_pwr_on()
76 	mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);  in imx_set_cpu_pwr_on()
78 	mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id));  in imx_set_cpu_pwr_on()
81 	while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0)  in imx_set_cpu_pwr_on()
85 	mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);  in imx_set_cpu_pwr_on()
87 	mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id));  in imx_set_cpu_pwr_on()
90 void imx_set_cpu_lpm(unsigned int core_id, bool pdn)  in imx_set_cpu_lpm()  argument
96 		mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |  in imx_set_cpu_lpm()
97 				COREx_IRQ_WUP(core_id));  in imx_set_cpu_lpm()
99 		mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);  in imx_set_cpu_lpm()
102 		mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |  in imx_set_cpu_lpm()
103 				COREx_IRQ_WUP(core_id));  in imx_set_cpu_lpm()
105 		mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);  in imx_set_cpu_lpm()