Searched refs:coherent (Results 1 – 16 of 16) sorted by relevance
242 * The base address of the coherent memory section must be page-aligned (4K)243 * to guarantee that the coherent data are stored on their own pages and245 * memory attributes for the coherent data page tables.250 * Bakery locks are stored in coherent memory
140 dma-coherent;152 dma-coherent;163 dma-coherent;186 dma-coherent;
66 dma-coherent;77 dma-coherent;
151 dma-coherent;158 dma-coherent;
151 dma-coherent;162 dma-coherent;187 dma-coherent;198 dma-coherent;
375 dma-coherent;381 dma-coherent;
526 dma-coherent;538 dma-coherent;
151 sc_bool_t grant, sc_bool_t coherent);
7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
33 sc_bool_t grant, sc_bool_t coherent) in sc_rm_partition_alloc() argument45 RPC_U8(&msg, 4U) = (uint8_t)coherent; in sc_rm_partition_alloc()
1729 - The coherent memory section (if enabled) must be zero-initialised as well.1730 - The MMU setup code needs to know the extents of the coherent and read-only2196 Use of coherent memory in TF-A2205 TF-A defines coherent memory as a region of memory with Device nGnRE attributes2207 is the smallest possible size of the coherent memory region.2210 mismatched attributes from various CPUs are allocated in a coherent memory2211 region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory2223 Disabling the use of coherent memory in TF-A2226 It might be desirable to avoid the cost of allocating coherent memory on2227 platforms which are memory constrained. TF-A enables inclusion of coherent[all …]
88 This flag determines whether to include the coherent memory region in the
1113 | plat_ncoh_region | 64 | memory_info | Device non-coherent ranges Info structure |1115 | plat_coh_region | 88 | memory_info | Device coherent ranges Info structure |
1020 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be1162 - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
1691 …- is OCM configured as coherent ([c3ab09d](https://review.trustedfirmware.org/plugins/gitiles/TF-A…5118 …- add device mapping for coherent memory ([cef2e92](https://review.trustedfirmware.org/plugins/git…6298 …- make coherent memory section optional ([af994ae](https://review.trustedfirmware.org/plugins/giti…10877 - ti: k3: drivers: ti_sci: Put sequence number in coherent memory and remove11077 - ti/k3: common: Add support for J721E, Use coherent memory for shared data,12681 - The bakery lock structure for coherent memory has been optimised.12828 memory as coherent. The build flag `USE_COHERENT_MEM` can be used to choose12833 coherent memory has been added.12834 - Memory which was previously marked as coherent is now kept coherent through12958 - Removed coherent stacks from the codebase. Stacks allocated in normal memory[all …]
82 page boundary (4K) for each BL stage. All sections which allocate coherent520 the platform decides not to use the coherent memory section by undefining the