Lines Matching refs:coherent

1729 -  The coherent memory section (if enabled) must be zero-initialised as well.
1730 -  The MMU setup code needs to know the extents of the coherent and read-only
2196 Use of coherent memory in TF-A
2205 TF-A defines coherent memory as a region of memory with Device nGnRE attributes
2207 is the smallest possible size of the coherent memory region.
2210 mismatched attributes from various CPUs are allocated in a coherent memory
2211 region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory
2223 Disabling the use of coherent memory in TF-A
2226 It might be desirable to avoid the cost of allocating coherent memory on
2227 platforms which are memory constrained. TF-A enables inclusion of coherent
2232 The below sections analyze the data structures allocated in the coherent memory
2240 structure is allocated in the coherent memory region in TF-A because it can be
2275 them from coherent memory involves only doing a clean and invalidate of the
2286 The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2311 cache maintenance is not enough to allocate them in coherent memory. Consider
2396 Non Functional Impact of removing coherent memory
2399 Removal of the coherent memory region leads to the additional software overhead
2418 whether coherent memory should be used. If a platform disables