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Searched refs:cmd (Results 1 – 25 of 93) sorted by relevance

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/rk3399_ARM-atf/plat/socionext/synquacer/drivers/scpi/
H A Dsq_scpi.c48 static void scpi_secure_message_receive(scpi_cmd_t *cmd) in scpi_secure_message_receive() argument
52 assert(cmd != NULL); in scpi_secure_message_receive()
70 memcpy(cmd, (void *) SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd)); in scpi_secure_message_receive()
119 scpi_cmd_t *cmd; in scpi_set_sq_power_state() local
132 cmd = SCPI_CMD_HEADER_AP_TO_SCP; in scpi_set_sq_power_state()
133 cmd->id = SCPI_CMD_SET_POWER_STATE; in scpi_set_sq_power_state()
134 cmd->set = SCPI_SET_NORMAL; in scpi_set_sq_power_state()
135 cmd->sender = 0; in scpi_set_sq_power_state()
136 cmd->size = sizeof(state); in scpi_set_sq_power_state()
151 scpi_cmd_t *cmd; in scpi_sys_power_state() local
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/rk3399_ARM-atf/drivers/brcm/
H A Dspi_flash.c43 static void spi_flash_addr(uint32_t addr, uint8_t *cmd) in spi_flash_addr() argument
49 cmd[1] = addr >> 16; in spi_flash_addr()
50 cmd[2] = addr >> 8; in spi_flash_addr()
51 cmd[3] = addr >> 0; in spi_flash_addr()
86 uint8_t cmd; in spi_flash_cmd_wait() local
93 cmd = CMD_RDSR; in spi_flash_cmd_wait()
94 ret = spi_flash_cmd_read(&cmd, 1, &status, 1); in spi_flash_cmd_wait()
114 static int spi_flash_write_common(struct spi_flash *flash, const uint8_t *cmd, in spi_flash_write_common() argument
126 ret = spi_flash_cmd_write(cmd, cmd_len, buf, buf_len); in spi_flash_write_common()
141 static int spi_flash_read_common(const uint8_t *cmd, size_t cmd_len, in spi_flash_read_common() argument
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H A Dspi_sf.c14 static int spi_flash_read_write(const uint8_t *cmd, in spi_flash_read_write() argument
26 ret = spi_xfer(cmd_len * BITS_PER_BYTE, cmd, NULL, flags); in spi_flash_read_write()
41 int spi_flash_cmd_read(const uint8_t *cmd, in spi_flash_cmd_read() argument
46 return spi_flash_read_write(cmd, cmd_len, NULL, data, data_len); in spi_flash_cmd_read()
49 int spi_flash_cmd(uint8_t cmd, void *response, size_t len) in spi_flash_cmd() argument
51 return spi_flash_cmd_read(&cmd, CMD_LEN1, response, len); in spi_flash_cmd()
54 int spi_flash_cmd_write(const uint8_t *cmd, in spi_flash_cmd_write() argument
59 return spi_flash_read_write(cmd, cmd_len, data, NULL, data_len); in spi_flash_cmd_write()
/rk3399_ARM-atf/plat/brcm/common/
H A Dbrcm_scpi.c55 static void scpi_secure_message_receive(scpi_cmd_t *cmd) in scpi_secure_message_receive() argument
59 assert(cmd != NULL); in scpi_secure_message_receive()
77 memcpy(cmd, (void *) SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd)); in scpi_secure_message_receive()
128 scpi_cmd_t *cmd; in scpi_set_brcm_power_state() local
151 cmd = SCPI_CMD_HEADER_AP_TO_SCP; in scpi_set_brcm_power_state()
152 cmd->id = SCPI_CMD_SET_POWER_STATE; in scpi_set_brcm_power_state()
153 cmd->set = SCPI_SET_NORMAL; in scpi_set_brcm_power_state()
154 cmd->sender = 0; in scpi_set_brcm_power_state()
155 cmd->size = sizeof(state); in scpi_set_brcm_power_state()
181 scpi_cmd_t *cmd; in scpi_get_brcm_power_state() local
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/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_emmc.c98 struct uniphier_mmc_cmd *cmd) in uniphier_emmc_send_cmd() argument
106 mmio_write_32(host_base + SDHCI_ARGUMENT, cmd->cmdarg); in uniphier_emmc_send_cmd()
108 if (cmd->is_data) in uniphier_emmc_send_cmd()
115 if (!(cmd->resp_type & MMC_RSP_PRESENT)) in uniphier_emmc_send_cmd()
117 else if (cmd->resp_type & MMC_RSP_136) in uniphier_emmc_send_cmd()
119 else if (cmd->resp_type & MMC_RSP_BUSY) in uniphier_emmc_send_cmd()
124 if (cmd->resp_type & MMC_RSP_CRC) in uniphier_emmc_send_cmd()
126 if (cmd->resp_type & MMC_RSP_OPCODE) in uniphier_emmc_send_cmd()
128 if (cmd->is_data) in uniphier_emmc_send_cmd()
131 if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data) in uniphier_emmc_send_cmd()
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/rk3399_ARM-atf/drivers/arm/css/scpi/
H A Dcss_scpi.c54 static int scpi_secure_message_receive(scpi_cmd_t *cmd) in scpi_secure_message_receive() argument
58 assert(cmd != NULL); in scpi_secure_message_receive()
76 memcpy(cmd, (void *) SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd)); in scpi_secure_message_receive()
133 scpi_cmd_t *cmd; in scpi_set_css_power_state() local
156 cmd = SCPI_CMD_HEADER_AP_TO_SCP; in scpi_set_css_power_state()
157 cmd->id = SCPI_CMD_SET_CSS_POWER_STATE; in scpi_set_css_power_state()
158 cmd->set = SCPI_SET_NORMAL; in scpi_set_css_power_state()
159 cmd->sender = 0; in scpi_set_css_power_state()
160 cmd->size = sizeof(state); in scpi_set_css_power_state()
186 scpi_cmd_t *cmd; in scpi_get_css_power_state() local
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/rk3399_ARM-atf/drivers/st/mmc/
H A Dstm32_sdmmc2.c145 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd);
146 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd);
231 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) in stm32_sdmmc2_send_cmd_req() argument
240 if (cmd == NULL) { in stm32_sdmmc2_send_cmd_req()
245 arg_reg = cmd->cmd_arg; in stm32_sdmmc2_send_cmd_req()
251 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; in stm32_sdmmc2_send_cmd_req()
253 if (cmd->resp_type == 0U) { in stm32_sdmmc2_send_cmd_req()
257 if ((cmd->resp_type & MMC_RSP_48) != 0U) { in stm32_sdmmc2_send_cmd_req()
258 if ((cmd->resp_type & MMC_RSP_136) != 0U) { in stm32_sdmmc2_send_cmd_req()
261 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { in stm32_sdmmc2_send_cmd_req()
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/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/pmic_wrap/v1/
H A Dmt_spm_pmic_wrap.c32 cmd_addr = current_phase->cmd[idx].cmd_addr; in mt_spm_pmic_wrap_set_phase()
33 cmd_data = current_phase->cmd[idx].cmd_data; in mt_spm_pmic_wrap_set_phase()
35 mmio_write_32(current_phase->cmd[idx].spm_pwrap_addr, in mt_spm_pmic_wrap_set_phase()
57 current_phase->cmd[idx].cmd_data = cmd_data; in mt_spm_pmic_wrap_set_cmd()
58 cmd_addr = current_phase->cmd[idx].cmd_addr; in mt_spm_pmic_wrap_set_cmd()
60 mmio_write_32(current_phase->cmd[idx].spm_pwrap_addr, in mt_spm_pmic_wrap_set_cmd()
76 return pmic_wrap->phase[phase].cmd[idx].cmd_data; in mt_spm_pmic_wrap_get_cmd()
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dscp_cmd.c29 resp->cmd = code & SCP_CMD_MASK; in scp_read_response()
40 int scp_send_cmd(uint32_t cmd, uint32_t param, uint32_t timeout) in scp_send_cmd() argument
44 mmio_write_32(CRMU_MAIL_BOX0, cmd); in scp_send_cmd()
52 (scp_resp.cmd == cmd)) { in scp_send_cmd()
/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.c38 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
199 static bool is_data_transfer_to_card(const struct mmc_cmd *cmd) in is_data_transfer_to_card() argument
201 unsigned int cmd_idx = cmd->cmd_idx; in is_data_transfer_to_card()
206 static bool is_data_transfer_cmd(const struct mmc_cmd *cmd) in is_data_transfer_cmd() argument
209 unsigned int cmd_idx = cmd->cmd_idx; in is_data_transfer_cmd()
218 if ((ADTC_MASK_SD & BIT_32(cmd->cmd_idx)) != 0U) { in is_data_transfer_cmd()
225 static int get_xfr_type(const struct mmc_cmd *cmd, bool data, uint32_t *xfertype) in get_xfr_type() argument
227 *xfertype = XFERTYPE_CMD(cmd->cmd_idx); in get_xfr_type()
229 switch (cmd->resp_type) { in get_xfr_type()
250 ERROR("Invalid CMD response: %u\n", cmd->resp_type); in get_xfr_type()
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/rk3399_ARM-atf/drivers/cadence/emmc/
H A Dcdns_sdmmc.c23 int cdns_send_cmd(struct mmc_cmd *cmd);
542 int cdns_send_cmd(struct mmc_cmd *cmd) in cdns_send_cmd() argument
550 assert(cmd); in cdns_send_cmd()
554 if ((cmd->cmd_idx == SD_STOP_TRANSMISSION) && (!data_cmd)) { in cdns_send_cmd()
571 cmd_flags = (cmd->cmd_idx) << COM_IDX; in cdns_send_cmd()
573 if ((cmd->resp_type & MMC_RSP_136) != 0) { in cdns_send_cmd()
575 } else if (((cmd->resp_type & MMC_RSP_48) != 0) && in cdns_send_cmd()
576 ((cmd->resp_type & MMC_RSP_BUSY) != 0)) { in cdns_send_cmd()
578 } else if ((cmd->resp_type & MMC_RSP_48) != 0) { in cdns_send_cmd()
584 if ((cmd->resp_type & MMC_RSP_CRC) != 0) { in cdns_send_cmd()
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/rk3399_ARM-atf/plat/intel/soc/common/drivers/sdmmc/
H A Dsdmmc.c43 struct mmc_cmd cmd; in sdmmc_send_cmd() local
46 zeromem(&cmd, sizeof(struct mmc_cmd)); in sdmmc_send_cmd()
48 cmd.cmd_idx = idx; in sdmmc_send_cmd()
49 cmd.cmd_arg = arg; in sdmmc_send_cmd()
50 cmd.resp_type = r_type; in sdmmc_send_cmd()
52 ret = ops->send_cmd(&cmd); in sdmmc_send_cmd()
58 *r_data = cmd.resp_data[i]; in sdmmc_send_cmd()
/rk3399_ARM-atf/drivers/marvell/
H A Dmci.c319 int mci_read(int mci_idx, uint32_t cmd, uint32_t *value) in mci_read() argument
323 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_idx), cmd); in mci_read()
332 int mci_write(int mci_idx, uint32_t cmd, uint32_t data) in mci_write() argument
335 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_idx), cmd); in mci_write()
732 uint32_t cmd, data; in mci_get_link_status() local
734 cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_STATUS_REG_NUM) | in mci_get_link_status()
736 if (mci_read(0, cmd, &data)) { in mci_get_link_status()
752 uint32_t cmd, data; in mci_turn_link_down() local
758 cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | in mci_turn_link_down()
762 rval = mci_write(0, cmd, data); in mci_turn_link_down()
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/rk3399_ARM-atf/drivers/rpi3/sdhost/
H A Drpi3_sdhost.c21 static int rpi3_sdhost_send_cmd(struct mmc_cmd *cmd);
70 static void send_command_raw(unsigned int cmd, unsigned int arg) in send_command_raw() argument
84 rpi3_sdhost_params.current_cmd = cmd & HC_CMD_COMMAND_MASK; in send_command_raw()
88 mmio_write_32(reg_base + HC_COMMAND, cmd | HC_CMD_ENABLE); in send_command_raw()
99 static void send_command_decorated(unsigned int cmd, unsigned int arg) in send_command_decorated() argument
103 switch (cmd & HC_CMD_COMMAND_MASK) { in send_command_decorated()
127 send_command_raw(cmd | cmd_flags, arg); in send_command_decorated()
257 static int rpi3_sdhost_send_cmd(struct mmc_cmd *cmd) in rpi3_sdhost_send_cmd() argument
273 cmd_idx = cmd->cmd_idx & HC_CMD_COMMAND_MASK; in rpi3_sdhost_send_cmd()
275 cmd_arg = cmd->cmd_arg; in rpi3_sdhost_send_cmd()
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/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_pmic_lp.c85 static void mt_spm_dump_pmic_gs(uint32_t cmd) in mt_spm_dump_pmic_gs() argument
88 if (cmd & MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) { /*Suspend enter*/ in mt_spm_dump_pmic_gs()
92 if (cmd & MT_RM_CONSTRAINT_ALLOW_VCORE_LP) { in mt_spm_dump_pmic_gs()
93 if (cmd & MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF) { /*SODI3 enter*/ in mt_spm_dump_pmic_gs()
188 int do_spm_low_power(enum SPM_PWR_TYPE type, uint32_t cmd) in do_spm_low_power() argument
197 if (!(cmd & MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND)) in do_spm_low_power()
207 if (cmd & MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND) in do_spm_low_power()
234 mt_spm_dump_pmic_gs(cmd); in do_spm_low_power()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_pmic_lp.h34 int do_spm_low_power(enum SPM_PWR_TYPE type, uint32_t cmd);
66 static inline int do_spm_low_power(enum SPM_PWR_TYPE type, uint32_t cmd) in do_spm_low_power() argument
69 (void)cmd; in do_spm_low_power()
H A Dmt_spm_pmic_lp.c84 static void mt_spm_dump_pmic_gs(uint32_t cmd) in mt_spm_dump_pmic_gs() argument
87 if (cmd & MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) { /* Suspend enter */ in mt_spm_dump_pmic_gs()
92 if (cmd & MT_RM_CONSTRAINT_ALLOW_VCORE_LP) { in mt_spm_dump_pmic_gs()
93 if (cmd & MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF) { /* SODI3 */ in mt_spm_dump_pmic_gs()
209 int do_spm_low_power(enum SPM_PWR_TYPE type, uint32_t cmd) in do_spm_low_power() argument
219 if (cmd & MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND) { in do_spm_low_power()
239 if (!(cmd & MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND)) in do_spm_low_power()
251 if (cmd & MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND) in do_spm_low_power()
/rk3399_ARM-atf/drivers/renesas/common/emmc/
H A Demmc_utility.c126 void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg) in emmc_make_nontrans_cmd() argument
129 mmc_drv_obj.cmd_info.cmd = cmd; in emmc_make_nontrans_cmd()
133 cmd_reg_hw[cmd & HAL_MEMCARD_COMMAND_INDEX_MASK]; in emmc_make_nontrans_cmd()
144 switch (mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK) { in emmc_make_nontrans_cmd()
175 void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, in emmc_make_trans_cmd() argument
181 emmc_make_nontrans_cmd(cmd, arg); /* update common information */ in emmc_make_trans_cmd()
/rk3399_ARM-atf/plat/mediatek/drivers/dp/
H A Dmt_dp.c25 int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val) in dp_secure_handler() argument
33 if ((cmd > DP_ATF_CMD_COUNT) || (val == NULL)) { in dp_secure_handler()
34 INFO("dp_secure_handler error cmd 0x%" PRIx64 "\n", cmd); in dp_secure_handler()
38 switch (cmd) { in dp_secure_handler()
/rk3399_ARM-atf/drivers/mtd/nand/
H A Dspi_nand.c36 op.cmd.opcode = SPI_NAND_OP_GET_FEATURE; in spi_nand_reg()
38 op.cmd.opcode = SPI_NAND_OP_SET_FEATURE; in spi_nand_reg()
41 op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; in spi_nand_reg()
133 op.cmd.opcode = SPI_NAND_OP_RESET; in spi_nand_reset()
134 op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; in spi_nand_reset()
149 op.cmd.opcode = SPI_NAND_OP_READ_ID; in spi_nand_read_id()
150 op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; in spi_nand_read_id()
169 op.cmd.opcode = SPI_NAND_OP_LOAD_PAGE; in spi_nand_load_page()
170 op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; in spi_nand_load_page()
276 spinand_dev.spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE; in spi_nand_init()
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/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/mcdi/
H A Dmtk_mcdi.c169 uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD); in mcdi_hotplug_clr() local
172 if (!(cmd & tgt)) in mcdi_hotplug_clr()
179 cmd &= ~tgt; in mcdi_hotplug_clr()
180 mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd); in mcdi_hotplug_clr()
187 uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD); in mcdi_hotplug_set() local
190 if ((cmd & tgt) == tgt) in mcdi_hotplug_set()
197 cmd |= tgt; in mcdi_hotplug_set()
198 mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd); in mcdi_hotplug_set()
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/bpmp_ipc/
H A Dintf.h70 uint32_t cmd; member
125 #define make_mrq_clk_cmd(cmd, id) (((cmd) << 24) | (id & 0xFFFFFF)) argument
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/constraints/
H A Dmt_spm_rc_syspll.c50 static uint32_t cmd; variable
149 cmd = CONSTRAINT_SYSPLL_ALLOW; in spm_run_rc_syspll()
152 cmd |= MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND; in spm_run_rc_syspll()
167 do_spm_low_power(SPM_LP_ENTER, cmd); in spm_run_rc_syspll()
173 mt_spm_sspm_notify_u32(nb_type, cmd); in spm_run_rc_syspll()
213 do_spm_low_power(SPM_LP_RESUME, cmd); in spm_reset_rc_syspll()
219 mt_spm_sspm_notify_u32(nb_type, cmd); in spm_reset_rc_syspll()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/constraints/
H A Dmt_spm_rc_syspll.c49 static uint32_t cmd; variable
144 cmd = CONSTRAINT_SYSPLL_ALLOW; in spm_run_rc_syspll()
147 cmd |= MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND; in spm_run_rc_syspll()
160 if (do_spm_low_power(SPM_LP_ENTER, cmd) == PMIC_ONLV) in spm_run_rc_syspll()
167 mt_spm_sspm_notify_u32(nb_type, cmd); in spm_run_rc_syspll()
204 do_spm_low_power(SPM_LP_RESUME, cmd); in spm_reset_rc_syspll()
210 mt_spm_sspm_notify_u32(nb_type, cmd); in spm_reset_rc_syspll()
/rk3399_ARM-atf/drivers/ufs/
H A Dufs.c161 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd) in ufshc_send_uic_cmd() argument
166 if (base == 0 || cmd == NULL) in ufshc_send_uic_cmd()
181 mmio_write_32(base + UCMDARG1, cmd->arg1); in ufshc_send_uic_cmd()
182 mmio_write_32(base + UCMDARG2, cmd->arg2); in ufshc_send_uic_cmd()
183 mmio_write_32(base + UCMDARG3, cmd->arg3); in ufshc_send_uic_cmd()
184 mmio_write_32(base + UICCMD, cmd->op); in ufshc_send_uic_cmd()
187 cmd->op == DME_SET); in ufshc_send_uic_cmd()
199 uic_cmd_t cmd; in ufshc_dme_get() local
207 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); in ufshc_dme_get()
208 cmd.arg2 = 0; in ufshc_dme_get()
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