| #
1d64109e |
| 06-Jun-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st-fixes" into integration
* changes: fix(spi-nand): add Quad Enable management fix(st-clock): disabling CKPER clock is not functional on stm32mp13 fix(st-uart): skip
Merge changes from topic "st-fixes" into integration
* changes: fix(spi-nand): add Quad Enable management fix(st-clock): disabling CKPER clock is not functional on stm32mp13 fix(st-uart): skip console flush if UART is disabled fix(st): flush UART at the end of uart_read() fix(stm32mp1): use the BSEC nodes compatible for stm32mp13 fix(stm32mp13-fdts): correct the BSEC nodes compatible fix(stm32mp1-fdts): move /omit-if-no-ref/ to overlay files fix(stm32mp1): properly check PSCI functions return
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| #
da7a33cf |
| 27-Sep-2022 |
Christophe Kerello <christophe.kerello@foss.st.com> |
fix(spi-nand): add Quad Enable management
The framework currently supports QE feature only for Macronix devices. Kioxia devices also support this feature, but this feature can not be set based on th
fix(spi-nand): add Quad Enable management
The framework currently supports QE feature only for Macronix devices. Kioxia devices also support this feature, but this feature can not be set based on the manufacturer ID as Kioxia first SPI NAND generation does not support the QE feature when the second generation does.
Use a flag to manage QE feature. This flag will be added at board level to manage the device.
Change-Id: I7a3683a2df8739967b17b4abbec32c51bf206b93 Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
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| #
8d9c1b3c |
| 16-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st-format-signedness" into integration
* changes: feat(stm32mp1): enable format-signedness warning fix(stm32mp1): correct types in messages fix(st-pmic): correct verb
Merge changes from topic "st-format-signedness" into integration
* changes: feat(stm32mp1): enable format-signedness warning fix(stm32mp1): correct types in messages fix(st-pmic): correct verbose message fix(st-sdmmc2): correct cmd_idx type in messages fix(st-fmc): fix type in message fix(mtd): correct types in messages fix(usb): correct type in message fix(tzc400): correct message with filter fix(psci): correct parent_node type in messages fix(libc): correct some messages fix(fconf): correct image_id type in messages fix(bl2): correct messages with image_id
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| #
6e86b462 |
| 14-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(mtd): correct types in messages
Some messages don't use the correct types, update them. This avoids warning when -Wformat-signedness is enabled.
Change-Id: Ie5384a7d139c48a623e1617c93d15fecc8a3
fix(mtd): correct types in messages
Some messages don't use the correct types, update them. This avoids warning when -Wformat-signedness is enabled.
Change-Id: Ie5384a7d139c48a623e1617c93d15fecc8a36061 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
890ee3e8 |
| 30-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st_fixes" into integration
* changes: fix(stm32_console): do not skip init for crash console fix(plat/st): add UART reset in crash console init refactor(stm32mp1_clk)
Merge changes from topic "st_fixes" into integration
* changes: fix(stm32_console): do not skip init for crash console fix(plat/st): add UART reset in crash console init refactor(stm32mp1_clk): update RCC registers file fix(stm32mp1_clk): keep RTCAPB clock always on fix(stm32mp1_clk): fix RTC clock rating fix(stm32mp1_clk): correctly manage RTC clock source fix(spi_nand): check correct manufacturer id fix(spi_nand): check that parameters have been set
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| #
4490b796 |
| 18-Jun-2021 |
Christophe Kerello <christophe.kerello@foss.st.com> |
fix(spi_nand): check correct manufacturer id
On most of SPI NAND, the read id command needs a dummy byte, except GIGADEVICE SPI NAND that needs an address. To be compliant with all memories provider
fix(spi_nand): check correct manufacturer id
On most of SPI NAND, the read id command needs a dummy byte, except GIGADEVICE SPI NAND that needs an address. To be compliant with all memories providers, the first byte returns by the READ_ID command is not relevant (garbage).
Change-Id: Ife74ccab333dd1a04799abe230d3f07fa6ea1edb Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| #
bc453ab1 |
| 18-Jun-2021 |
Christophe Kerello <christophe.kerello@foss.st.com> |
fix(spi_nand): check that parameters have been set
This patch checks that the SPI NAND parameters needed by the framework have been set before starting to read data.
Change-Id: I17b36606701c44864dc
fix(spi_nand): check that parameters have been set
This patch checks that the SPI NAND parameters needed by the framework have been set before starting to read data.
Change-Id: I17b36606701c44864dcf1783f810da5c8cbf88f2 Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| #
0a910952 |
| 20-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "ld/mtd_framework" into integration
* changes: doc: stm32mp1: Update build command line fdts: stm32mp1: remove second QSPI flash instance stm32mp1: Add support for SPI
Merge changes from topic "ld/mtd_framework" into integration
* changes: doc: stm32mp1: Update build command line fdts: stm32mp1: remove second QSPI flash instance stm32mp1: Add support for SPI-NOR boot device stm32mp1: Add support for SPI-NAND boot device spi: stm32_qspi: Add QSPI support fdts: stm32mp1: update for FMC2 pin muxing stm32mp1: Add support for raw NAND boot device fmc: stm32_fmc2_nand: Add FMC2 driver support stm32mp1: Reduce MAX_XLAT_TABLES to 4 io: stm32image: fix device_size type stm32mp: add DT helper for reg by name stm32mp1: add compilation flags for boot devices lib: utils_def: add CLAMP macro compiler_rt: Import popcountdi2.c and popcountsi2.c files Add SPI-NOR framework Add SPI-NAND framework Add SPI-MEM framework Add raw NAND framework
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| #
c3e57739 |
| 25-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
Add SPI-NAND framework
This framework supports SPI-NAND and is based on the SPI-MEM framework for SPI operations. It uses a common high level access using the io_mtd.
It is limited to the read func
Add SPI-NAND framework
This framework supports SPI-NAND and is based on the SPI-MEM framework for SPI operations. It uses a common high level access using the io_mtd.
It is limited to the read functionalities.
Default behavior is the basic one data line operation but it could be overridden by platform.
Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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