xref: /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/mt_spm_pmic_lp.h (revision cf2df874cd09305ac7282fadb0fef6be597dfffb)
1*e8e87683SWenzhen Yu /*
2*e8e87683SWenzhen Yu  * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3*e8e87683SWenzhen Yu  *
4*e8e87683SWenzhen Yu  * SPDX-License-Identifier: BSD-3-Clause
5*e8e87683SWenzhen Yu  */
6*e8e87683SWenzhen Yu 
7*e8e87683SWenzhen Yu #ifndef MT_SPM_PMIC_LP_H
8*e8e87683SWenzhen Yu #define MT_SPM_PMIC_LP_H
9*e8e87683SWenzhen Yu 
10*e8e87683SWenzhen Yu enum SPM_PWR_TYPE {
11*e8e87683SWenzhen Yu 	SPM_LP_ENTER,
12*e8e87683SWenzhen Yu 	SPM_LP_RESUME
13*e8e87683SWenzhen Yu };
14*e8e87683SWenzhen Yu 
15*e8e87683SWenzhen Yu enum {
16*e8e87683SWenzhen Yu 	LP_MT6363 = 0,
17*e8e87683SWenzhen Yu 	LP_MT6373,
18*e8e87683SWenzhen Yu 	LP_MT6316_1,
19*e8e87683SWenzhen Yu 	LP_MT6316_2,
20*e8e87683SWenzhen Yu 	LP_MT6316_3,
21*e8e87683SWenzhen Yu 	LP_MT6316_4,
22*e8e87683SWenzhen Yu 	LP_PMIC_SLAVE_NUM,
23*e8e87683SWenzhen Yu };
24*e8e87683SWenzhen Yu 
25*e8e87683SWenzhen Yu #ifdef MTK_SPM_PMIC_LP_SUPPORT
26*e8e87683SWenzhen Yu void set_vcore_lp_enable(bool enable);
27*e8e87683SWenzhen Yu bool get_vcore_lp_enable(void);
28*e8e87683SWenzhen Yu 
29*e8e87683SWenzhen Yu void set_vsram_lp_enable(bool enable);
30*e8e87683SWenzhen Yu bool get_vsram_lp_enable(void);
31*e8e87683SWenzhen Yu void set_vsram_lp_volt(uint32_t volt);
32*e8e87683SWenzhen Yu uint32_t get_vsram_lp_volt(void);
33*e8e87683SWenzhen Yu 
34*e8e87683SWenzhen Yu int do_spm_low_power(enum SPM_PWR_TYPE type, uint32_t cmd);
35*e8e87683SWenzhen Yu #else
set_vcore_lp_enable(bool enable)36*e8e87683SWenzhen Yu static inline void set_vcore_lp_enable(bool enable)
37*e8e87683SWenzhen Yu {
38*e8e87683SWenzhen Yu 	(void)enable;
39*e8e87683SWenzhen Yu }
40*e8e87683SWenzhen Yu 
get_vcore_lp_enable(void)41*e8e87683SWenzhen Yu static inline bool get_vcore_lp_enable(void)
42*e8e87683SWenzhen Yu {
43*e8e87683SWenzhen Yu 	return false;
44*e8e87683SWenzhen Yu }
45*e8e87683SWenzhen Yu 
set_vsram_lp_enable(bool enable)46*e8e87683SWenzhen Yu static inline void set_vsram_lp_enable(bool enable)
47*e8e87683SWenzhen Yu {
48*e8e87683SWenzhen Yu 	(void)enable;
49*e8e87683SWenzhen Yu }
50*e8e87683SWenzhen Yu 
get_vsram_lp_enable(void)51*e8e87683SWenzhen Yu static inline bool get_vsram_lp_enable(void)
52*e8e87683SWenzhen Yu {
53*e8e87683SWenzhen Yu 	return false;
54*e8e87683SWenzhen Yu }
55*e8e87683SWenzhen Yu 
set_vsram_lp_volt(uint32_t volt)56*e8e87683SWenzhen Yu static inline void set_vsram_lp_volt(uint32_t volt)
57*e8e87683SWenzhen Yu {
58*e8e87683SWenzhen Yu 	(void)volt;
59*e8e87683SWenzhen Yu }
60*e8e87683SWenzhen Yu 
get_vsram_lp_volt(void)61*e8e87683SWenzhen Yu static inline uint32_t get_vsram_lp_volt(void)
62*e8e87683SWenzhen Yu {
63*e8e87683SWenzhen Yu 	return 0;
64*e8e87683SWenzhen Yu }
65*e8e87683SWenzhen Yu 
do_spm_low_power(enum SPM_PWR_TYPE type,uint32_t cmd)66*e8e87683SWenzhen Yu static inline int do_spm_low_power(enum SPM_PWR_TYPE type, uint32_t cmd)
67*e8e87683SWenzhen Yu {
68*e8e87683SWenzhen Yu 	(void)type;
69*e8e87683SWenzhen Yu 	(void)cmd;
70*e8e87683SWenzhen Yu 	return 0;
71*e8e87683SWenzhen Yu }
72*e8e87683SWenzhen Yu #endif /* MTK_SPM_PMIC_LP_SUPPORT */
73*e8e87683SWenzhen Yu 
74*e8e87683SWenzhen Yu #endif /* MT_SPM_PMIC_LP_H */
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