1*e2469d82SVarun Wadekar /* 2*e2469d82SVarun Wadekar * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. 3*e2469d82SVarun Wadekar * 4*e2469d82SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*e2469d82SVarun Wadekar */ 6*e2469d82SVarun Wadekar 7*e2469d82SVarun Wadekar #ifndef BPMP_INTF_H 8*e2469d82SVarun Wadekar #define BPMP_INTF_H 9*e2469d82SVarun Wadekar 10*e2469d82SVarun Wadekar /** 11*e2469d82SVarun Wadekar * Flags used in IPC req 12*e2469d82SVarun Wadekar */ 13*e2469d82SVarun Wadekar #define FLAG_DO_ACK (U(1) << 0) 14*e2469d82SVarun Wadekar #define FLAG_RING_DOORBELL (U(1) << 1) 15*e2469d82SVarun Wadekar 16*e2469d82SVarun Wadekar /* Bit 1 is designated for CCPlex in secure world */ 17*e2469d82SVarun Wadekar #define HSP_MASTER_CCPLEX_BIT (U(1) << 1) 18*e2469d82SVarun Wadekar /* Bit 19 is designated for BPMP in non-secure world */ 19*e2469d82SVarun Wadekar #define HSP_MASTER_BPMP_BIT (U(1) << 19) 20*e2469d82SVarun Wadekar /* Timeout to receive response from BPMP is 1 sec */ 21*e2469d82SVarun Wadekar #define TIMEOUT_RESPONSE_FROM_BPMP_US U(1000000) /* in microseconds */ 22*e2469d82SVarun Wadekar 23*e2469d82SVarun Wadekar /** 24*e2469d82SVarun Wadekar * IVC protocol defines and command/response frame 25*e2469d82SVarun Wadekar */ 26*e2469d82SVarun Wadekar 27*e2469d82SVarun Wadekar /** 28*e2469d82SVarun Wadekar * IVC specific defines 29*e2469d82SVarun Wadekar */ 30*e2469d82SVarun Wadekar #define IVC_CMD_SZ_BYTES U(128) 31*e2469d82SVarun Wadekar #define IVC_DATA_SZ_BYTES U(120) 32*e2469d82SVarun Wadekar 33*e2469d82SVarun Wadekar /** 34*e2469d82SVarun Wadekar * Holds frame data for an IPC request 35*e2469d82SVarun Wadekar */ 36*e2469d82SVarun Wadekar struct frame_data { 37*e2469d82SVarun Wadekar /* Identification as to what kind of data is being transmitted */ 38*e2469d82SVarun Wadekar uint32_t mrq; 39*e2469d82SVarun Wadekar 40*e2469d82SVarun Wadekar /* Flags for slave as to how to respond back */ 41*e2469d82SVarun Wadekar uint32_t flags; 42*e2469d82SVarun Wadekar 43*e2469d82SVarun Wadekar /* Actual data being sent */ 44*e2469d82SVarun Wadekar uint8_t data[IVC_DATA_SZ_BYTES]; 45*e2469d82SVarun Wadekar }; 46*e2469d82SVarun Wadekar 47*e2469d82SVarun Wadekar /** 48*e2469d82SVarun Wadekar * Commands send to the BPMP firmware 49*e2469d82SVarun Wadekar */ 50*e2469d82SVarun Wadekar 51*e2469d82SVarun Wadekar /** 52*e2469d82SVarun Wadekar * MRQ command codes 53*e2469d82SVarun Wadekar */ 54*e2469d82SVarun Wadekar #define MRQ_RESET U(20) 55*e2469d82SVarun Wadekar #define MRQ_CLK U(22) 56*e2469d82SVarun Wadekar 57*e2469d82SVarun Wadekar /** 58*e2469d82SVarun Wadekar * Reset sub-commands 59*e2469d82SVarun Wadekar */ 60*e2469d82SVarun Wadekar #define CMD_RESET_ASSERT U(1) 61*e2469d82SVarun Wadekar #define CMD_RESET_DEASSERT U(2) 62*e2469d82SVarun Wadekar #define CMD_RESET_MODULE U(3) 63*e2469d82SVarun Wadekar 64*e2469d82SVarun Wadekar /** 65*e2469d82SVarun Wadekar * Used by the sender of an #MRQ_RESET message to request BPMP to 66*e2469d82SVarun Wadekar * assert or deassert a given reset line. 67*e2469d82SVarun Wadekar */ 68*e2469d82SVarun Wadekar struct __attribute__((packed)) mrq_reset_request { 69*e2469d82SVarun Wadekar /* reset action to perform (mrq_reset_commands) */ 70*e2469d82SVarun Wadekar uint32_t cmd; 71*e2469d82SVarun Wadekar /* id of the reset to affected */ 72*e2469d82SVarun Wadekar uint32_t reset_id; 73*e2469d82SVarun Wadekar }; 74*e2469d82SVarun Wadekar 75*e2469d82SVarun Wadekar /** 76*e2469d82SVarun Wadekar * MRQ_CLK sub-commands 77*e2469d82SVarun Wadekar * 78*e2469d82SVarun Wadekar */ 79*e2469d82SVarun Wadekar enum { 80*e2469d82SVarun Wadekar CMD_CLK_GET_RATE = U(1), 81*e2469d82SVarun Wadekar CMD_CLK_SET_RATE = U(2), 82*e2469d82SVarun Wadekar CMD_CLK_ROUND_RATE = U(3), 83*e2469d82SVarun Wadekar CMD_CLK_GET_PARENT = U(4), 84*e2469d82SVarun Wadekar CMD_CLK_SET_PARENT = U(5), 85*e2469d82SVarun Wadekar CMD_CLK_IS_ENABLED = U(6), 86*e2469d82SVarun Wadekar CMD_CLK_ENABLE = U(7), 87*e2469d82SVarun Wadekar CMD_CLK_DISABLE = U(8), 88*e2469d82SVarun Wadekar CMD_CLK_GET_ALL_INFO = U(14), 89*e2469d82SVarun Wadekar CMD_CLK_GET_MAX_CLK_ID = U(15), 90*e2469d82SVarun Wadekar CMD_CLK_MAX, 91*e2469d82SVarun Wadekar }; 92*e2469d82SVarun Wadekar 93*e2469d82SVarun Wadekar /** 94*e2469d82SVarun Wadekar * Used by the sender of an #MRQ_CLK message to control clocks. The 95*e2469d82SVarun Wadekar * clk_request is split into several sub-commands. Some sub-commands 96*e2469d82SVarun Wadekar * require no additional data. Others have a sub-command specific 97*e2469d82SVarun Wadekar * payload 98*e2469d82SVarun Wadekar * 99*e2469d82SVarun Wadekar * |sub-command |payload | 100*e2469d82SVarun Wadekar * |----------------------------|-----------------------| 101*e2469d82SVarun Wadekar * |CMD_CLK_GET_RATE |- | 102*e2469d82SVarun Wadekar * |CMD_CLK_SET_RATE |clk_set_rate | 103*e2469d82SVarun Wadekar * |CMD_CLK_ROUND_RATE |clk_round_rate | 104*e2469d82SVarun Wadekar * |CMD_CLK_GET_PARENT |- | 105*e2469d82SVarun Wadekar * |CMD_CLK_SET_PARENT |clk_set_parent | 106*e2469d82SVarun Wadekar * |CMD_CLK_IS_ENABLED |- | 107*e2469d82SVarun Wadekar * |CMD_CLK_ENABLE |- | 108*e2469d82SVarun Wadekar * |CMD_CLK_DISABLE |- | 109*e2469d82SVarun Wadekar * |CMD_CLK_GET_ALL_INFO |- | 110*e2469d82SVarun Wadekar * |CMD_CLK_GET_MAX_CLK_ID |- | 111*e2469d82SVarun Wadekar * 112*e2469d82SVarun Wadekar */ 113*e2469d82SVarun Wadekar struct mrq_clk_request { 114*e2469d82SVarun Wadekar /** 115*e2469d82SVarun Wadekar * sub-command and clock id concatenated to 32-bit word. 116*e2469d82SVarun Wadekar * - bits[31..24] is the sub-cmd. 117*e2469d82SVarun Wadekar * - bits[23..0] is the clock id 118*e2469d82SVarun Wadekar */ 119*e2469d82SVarun Wadekar uint32_t cmd_and_id; 120*e2469d82SVarun Wadekar }; 121*e2469d82SVarun Wadekar 122*e2469d82SVarun Wadekar /** 123*e2469d82SVarun Wadekar * Macro to prepare the MRQ_CLK sub-command 124*e2469d82SVarun Wadekar */ 125*e2469d82SVarun Wadekar #define make_mrq_clk_cmd(cmd, id) (((cmd) << 24) | (id & 0xFFFFFF)) 126*e2469d82SVarun Wadekar 127*e2469d82SVarun Wadekar #endif /* BPMP_INTF_H */ 128