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Searched refs:clk (Results 1 – 25 of 56) sorted by relevance

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/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk.mk8 -I${PLAT_DRIVERS_INCLUDE_PATH}/clk/s32cc \
9 -I${PLAT_DRIVERS_PATH}/clk/s32cc/include \
12 ${PLAT_DRIVERS_PATH}/clk/s32cc/mc_rgm.c \
13 ${PLAT_DRIVERS_PATH}/clk/s32cc/mc_me.c \
14 ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
15 ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_modules.c \
16 ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_utils.c \
17 ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_early_clks.c \
18 drivers/clk/clk.c \
H A Ds32cc_clk_utils.c34 struct s32cc_clk *clk; in s32cc_get_clk_from_table() local
38 clk = s32cc_clk_get_from_array(clk_arr[i], clk_id); in s32cc_get_clk_from_table()
39 if (clk != NULL) { in s32cc_get_clk_from_table()
40 return clk; in s32cc_get_clk_from_table()
48 size_t size, const struct s32cc_clk *clk, in s32cc_get_id_from_table() argument
55 if (clk_arr[i]->clks[j] != clk) { in s32cc_get_id_from_table()
H A Ds32cc_clk_drv.c81 const struct s32cc_clk *clk = s32cc_obj2clk(module); in get_clk_parent() local
83 if (clk->module != NULL) { in get_clk_parent()
84 return clk->module; in get_clk_parent()
87 if (clk->pclock != NULL) { in get_clk_parent()
88 return &clk->pclock->desc; in get_clk_parent()
249 const struct s32cc_clk *clk; in get_pll_mux() local
261 clk = s32cc_obj2clk(source); in get_pll_mux()
263 if (clk->module == NULL) { in get_pll_mux()
268 source = clk->module; in get_pll_mux()
706 struct s32cc_clk *clk; in get_mux_parent() local
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/rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/
H A Dregs.c18 static inline unsigned int cal_cwl(const unsigned long clk) in cal_cwl() argument
20 const unsigned int mclk_ps = get_memory_clk_ps(clk); in cal_cwl()
89 static void cal_timing_cfg(const unsigned long clk, in cal_timing_cfg() argument
97 const unsigned int mclk_ps = get_memory_clk_ps(clk); in cal_timing_cfg()
108 int trwt_mclk = (clk / 1000000 > 1900) ? 3 : 2; in cal_timing_cfg()
112 const int act_pd_exit_mclk = picos_to_mclk(clk, txp); in cal_timing_cfg()
119 const int tmrd_mclk = max(24U, picos_to_mclk(clk, 15000)); in cal_timing_cfg()
120 const int pretoact_mclk = picos_to_mclk(clk, pdimm->trp_ps); in cal_timing_cfg()
121 const int acttopre_mclk = picos_to_mclk(clk, pdimm->tras_ps); in cal_timing_cfg()
122 const int acttorw_mclk = picos_to_mclk(clk, pdimm->trcd_ps); in cal_timing_cfg()
[all …]
H A Dddr.c262 static int cal_odt(const unsigned int clk, in cal_odt() argument
323 static int cal_opts(const unsigned int clk, in cal_opts() argument
375 popts->bstopre = picos_to_mclk(clk, pdimm->refresh_rate_ps) >> 2; in cal_opts()
436 const unsigned long speed = priv->clk / 1000000; in cal_board_params()
478 ret = cal_odt(priv->clk, in synthesize_ctlr()
487 ret = cal_opts(priv->clk, in synthesize_ctlr()
805 ret = compute_ddrc(priv->clk, in cal_ddrc_regs()
826 ret = ddrc_set_regs(priv->clk, &priv->ddr_reg, priv->ddr[i], 0); in write_ddrc_regs()
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.c61 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_oscillator_get_data() local
62 struct stm32_osc_cfg *osc_cfg = clk->clock_cfg; in clk_oscillator_get_data()
161 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_gate_enable() local
162 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_enable()
171 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_gate_disable() local
172 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_disable()
179 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_gate_is_enabled() local
180 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_is_enabled()
229 const struct clk_stm32 *clk = _clk_get(priv, id); in _clk_get_ops() local
231 assert(clk->ops != NO_OPS); in _clk_get_ops()
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/rk3399_ARM-atf/include/drivers/nxp/clk/s32cc/
H A Ds32cc-clk-utils.h16 size_t size, const struct s32cc_clk *clk,
20 int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id);
H A Ds32cc-clk-modules.h324 static inline bool is_s32cc_clk_mux(const struct s32cc_clk *clk) in is_s32cc_clk_mux() argument
328 module = clk->module; in is_s32cc_clk_mux()
345 static inline struct s32cc_clkmux *s32cc_clk2mux(const struct s32cc_clk *clk) in s32cc_clk2mux() argument
347 if (!is_s32cc_clk_mux(clk)) { in s32cc_clk2mux()
351 return s32cc_obj2clkmux(clk->module); in s32cc_clk2mux()
/rk3399_ARM-atf/plat/imx/common/include/sci/svc/pm/
H A Dsci_pm_api.h454 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
475 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
503 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
527 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
548 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/rk3399_ARM-atf/include/drivers/nxp/ddr/
H A Dddr.h89 unsigned long clk; member
128 int compute_ddrc(const unsigned long clk,
135 int ddrc_set_regs(const unsigned long clk,
H A Dutility.h19 unsigned int get_memory_clk_ps(unsigned long clk);
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_private.h15 #define EMMC_INIT_PARAMS(base, clk) \ argument
17 .clk_rate = (clk), \
/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.c39 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
111 static int imx_usdhc_set_clk(unsigned int clk) in imx_usdhc_set_clk() argument
119 assert(clk > 0); in imx_usdhc_set_clk()
121 while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256) in imx_usdhc_set_clk()
124 while (((sdhc_clk / (div * pre_div)) > clk) && (div < 16U)) { in imx_usdhc_set_clk()
130 clk = (pre_div << 8) | (div << 4); in imx_usdhc_set_clk()
141 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); in imx_usdhc_set_clk()
399 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width) in imx_usdhc_set_ios() argument
404 ret = imx_usdhc_set_clk(clk); in imx_usdhc_set_ios()
/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/
H A Dboot_init_dram_config.c1770 void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) in boardcnf_get_brd_clk() argument
1775 *clk = 50; in boardcnf_get_brd_clk()
1781 *clk = 50; in boardcnf_get_brd_clk()
1785 *clk = 60; in boardcnf_get_brd_clk()
1789 *clk = 75; in boardcnf_get_brd_clk()
1793 *clk = 100; in boardcnf_get_brd_clk()
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/ls1046ardb/
H A Dddr_init.c171 const unsigned long clk = priv->clk / 1000000; in board_static_ddr() local
176 if (table[i].rate >= clk) { in board_static_ddr()
186 ERROR("Not static settings for rate %ld\n", clk); in board_static_ddr()
252 info.clk = get_ddr_freq(&sys, 0); in init_ddr()
/rk3399_ARM-atf/plat/imx/common/sci/svc/pm/
H A Dpm_rpc_clnt.c236 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) in sc_pm_set_clock_rate() argument
246 RPC_U8(&msg, 6U) = (uint8_t)clk; in sc_pm_set_clock_rate()
257 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) in sc_pm_get_clock_rate() argument
266 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_get_clock_rate()
280 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog) in sc_pm_clock_enable() argument
289 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_clock_enable()
301 sc_pm_clk_t clk, sc_pm_clk_parent_t parent) in sc_pm_set_clock_parent() argument
310 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_set_clock_parent()
321 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent) in sc_pm_get_clock_parent() argument
330 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_get_clock_parent()
/rk3399_ARM-atf/plat/xilinx/common/
H A Dplat_console.c52 consoleh->clk, in register_console()
59 consoleh->clk, in register_console()
251 boot_hd_console.clk = get_uart_clk(); in setup_console()
295 rt_hd_console.clk = get_uart_clk(); in setup_console()
/rk3399_ARM-atf/drivers/synopsys/emmc/
H A Ddw_mmc.c125 static int dw_set_ios(unsigned int clk, unsigned int width);
157 static void dw_set_clk(int clk) in dw_set_clk() argument
162 assert(clk > 0); in dw_set_clk()
165 if ((dw_params.clk_rate / (2 * div)) <= clk) { in dw_set_clk()
322 static int dw_set_ios(unsigned int clk, unsigned int width) in dw_set_ios() argument
338 dw_set_clk(clk); in dw_set_ios()
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_scmi.c459 struct stm32_scmi_clk *clk = &res->clock[j]; in stm32mp1_init_scmi_server() local
461 if ((clk->name == NULL) || in stm32mp1_init_scmi_server()
462 (strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE)) { in stm32mp1_init_scmi_server()
468 if (clk->enabled && in stm32mp1_init_scmi_server()
469 stm32mp_nsec_can_access_clock(clk->clock_id)) { in stm32mp1_init_scmi_server()
470 clk_enable(clk->clock_id); in stm32mp1_init_scmi_server()
/rk3399_ARM-atf/drivers/rpi3/sdhost/
H A Drpi3_sdhost.c22 static int rpi3_sdhost_set_ios(unsigned int clk, unsigned int width);
392 static int rpi3_sdhost_set_clock(unsigned int clk) in rpi3_sdhost_set_clock() argument
398 if (clk < 100000) { in rpi3_sdhost_set_clock()
404 div = max_clk / clk; in rpi3_sdhost_set_clock()
408 if ((max_clk / div) > clk) in rpi3_sdhost_set_clock()
424 static int rpi3_sdhost_set_ios(unsigned int clk, unsigned int width) in rpi3_sdhost_set_ios() argument
429 rpi3_sdhost_set_clock(clk); in rpi3_sdhost_set_ios()
430 VERBOSE("rpi3_sdhost: Changing clock to %dHz for data mode\n", clk); in rpi3_sdhost_set_ios()
/rk3399_ARM-atf/drivers/mmc/
H A Dmmc.c229 static int mmc_set_ios(unsigned int clk, unsigned int bus_width) in mmc_set_ios() argument
253 return ops->set_ios(clk, width); in mmc_set_ios()
476 static int mmc_enumerate(unsigned int clk, unsigned int bus_width) in mmc_enumerate() argument
550 ret = mmc_set_ios(clk, bus_width); in mmc_enumerate()
584 ret = ops->set_ios(clk, bus_width); in mmc_enumerate()
827 int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, in mmc_init() argument
839 (clk != 0) && in mmc_init()
850 return mmc_enumerate(clk, width); in mmc_init()
/rk3399_ARM-atf/drivers/st/uart/
H A Dstm32_uart.c311 int clk; in stm32_uart_init() local
340 clk = fdt_get_clock_id(uart_node); in stm32_uart_init()
341 if (clk < 0) { in stm32_uart_init()
344 clk_enable(clk); in stm32_uart_init()
/rk3399_ARM-atf/plat/nxp/soc-lx2160a/lx2160ardb/
H A Dddr_init.c190 info.clk = get_ddr_freq(&sys, 0); in init_ddr()
193 if (info.clk == 0) { in init_ddr()
194 info.clk = get_ddr_freq(&sys, 1); in init_ddr()
/rk3399_ARM-atf/drivers/renesas/common/scif/
H A Dscif.h10 int console_rcar_register(uintptr_t base, uint32_t clk, uint32_t baud,
/rk3399_ARM-atf/plat/xilinx/common/include/
H A Dplat_console.h23 uint32_t clk; member

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